Part Number: TDA4VM
I am trying to run two task on MCU2_1 main core 1) MCAN 7 instance 2) MCAN9 instance.
Both instances initialize with same parameter then wait for the interrupt cleared for new receive messages
When i send MCAN7 messages from Canoe first then its working fine then i trying to send MCAN9 messages then MCAN 9 gives some receiver error or When i send MCAN9 messages from Canoe first then its working fine then i trying to send MCAN7 messages then MCAN 7 gives some receiver error
/* ========================================================================== */
/* Header file inclusion */
/* ========================================================================== */
#include <canReceive.h>
// #include <ti/kernel/freertos/FreeRTOS-LTS/FreeRTOS-Kernel/include/FreeRTOS.h>
// #include <ti/kernel/freertos/FreeRTOS-LTS/FreeRTOS-Kernel/include/semphr.h>
//#include <ti/osal/MutexP.h>
/* ========================================================================== */
/* Macros */
/* ========================================================================== */
#define APP_ENABLE_UART_PRINT (0U)
#define APP_MCAN_STD_ID_FILT_START_ADDR (0U)
#define APP_MCAN_STD_ID_FILTER_NUM (1U)
#define APP_MCAN_EXT_ID_FILT_START_ADDR (48U)
#define APP_MCAN_EXT_ID_FILTER_NUM (1U)
#define APP_MCAN_TX_EVENT_START_ADDR (100U)
#define APP_MCAN_TX_EVENT_SIZE (5U)
#define APP_MCAN_TX_BUFF_START_ADDR (148U)
#define APP_MCAN_TX_BUFF_SIZE (5U)
#define APP_MCAN_TX_FIFO_SIZE (5U)
#define APP_MCAN_FIFO_0_START_ADDR (548U)
#define APP_MCAN_FIFO_0_NUM (64U)
#define APP_MCAN_FIFO_1_START_ADDR (748U)
#define APP_MCAN_FIFO_1_NUM (64U)
#define APP_MCAN_RX_BUFF_START_ADDR (948U)
#define APP_MCAN_EXT_ID_AND_MASK (0x1FFFFFFFU)
#define MCAN_PSR_BO_BUS_OFF (1U)
#define CAN_FD_OP_ENABLE (0x1U)
#define BAUD_RATE_SWITCH_ENABLE (0x1U)
#define TRANSMIT_PAUSE_DISABLED (0x0U)
#define EDGE_FILTRING_DISABLED (0x0U)
#define PROTOCOL_EXCEP_HANDLE_ENABLE (0x0U)
#define AUTOMATIC_RETRANSMISSION_DISABLED (0x1U)
#define WAKEUP_REQUEST_ENABLE (0x1U)
#define AUTO_WAKEUP_ENABLE (0x1U)
#define EMULATION_ENABLE (0x1U)
#define EMULATION_FAST_ACK_DISABLED (0x0U)
#define CLK_STOP_FAST_ACK_DISABLED (0x0U)
#define START_VAL_MESG_RAM_WATCHDOG_CNTR (0xFFU)
#define TRANS_DELAY_COMPENS_FILTER_WINDOW_LENGTH (0xAU)
#define TRANS_DELAY_COMPENS_OFFSET (0x6U)
#define TRANS_DELAY_COMPENS_ENABLE (0x1U)
#define BUS_MONITORING_MODE_DISABLED (0x0U)
#define NORMAL_CAN_OPERATION (0x0U)
#define TIMESTAMP_CNTR_PRESCALER (0xFU)
#define TIMESTAMP_SOURCE_SELECTTION (0x0U)
#define TIMEOUT_CNTR_DISABLED (0x0U)
#define START_VAL_TIMEOUT_DOWN_CNTR (0xFFFFU)
#define REJECT_REMOTE_FRAME_STD_ENABLE (0x1U)
#define REJECT_REMOTE_FRAME_EXT_ENABLE (0x1U)
#define REJECT_NONMATCHING_FRAME_EXT (0x2U)
#define REJECT_NONMATCHING_FRAME_STD (0x2U)
#define EXT_FILTER_TYPE_CLASSIC (0x2U)
#define EFEC_STORE_IN_RX_FIFO1 (0x2U)
#define EFID1_RECEIVE_ALL_ID_FILTER_VAL (0x0U)
#define EFID2_RECEIVE_ALL_ID_MASK_VAL (0x0U)
#define STD_FILTER_TYPE_CLASSIC (0x2U)
#define SFEC_STORE_IN_RX_FIFO1 (0x2U)
#define SFID1_RECEIVE_ALL_ID_FILTER_VAL (0x0U)
#define SFID2_RECEIVE_ALL_ID_MASK_VAL (0x0U)
#define NOMINAL_BR_PRESCALER (0x3U)
#define NOMINAL_TIMESEG1_BEFORE_SAMPLE_PNT (0x1EU)
#define NOMINAL_TIMESEG2_AFTER_SAMPLE_PNT (0x7U)
#define NOMINAL_SYNC_JUMP_WIDTH (0x8U)
#define DATA_BR_PRESCALER (0x3U)
#define DATA_TIMESEG1_BEFORE_SAMPLE_PNT (0x6U)
#define DATA_TIMESEG2_AFTER_SAMPLE_PNT (0x1U)
#define DATA_SYNC_JUMP_WIDTH (0x2U)
#define DEDICATED_TX_BUF_0 (0U)
#define TX_FIFO_OPERATION (0U)
#define TX_EVENT_FIFO_WATERMARK_INTR_3 (3U)
#define RX_EVENT_FIFO_0_WATERMARK_INTR_3 (3U)
#define RX_FIFO_0_BLOCKING_MODE (0U)
#define RX_EVENT_FIFO_1_WATERMARK_INTR_3 (3U)
#define RX_FIFO_1_BLOCKING_MODE (0U)
//main domain r5 core
#define APP_MAIN_MCAN_7_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_7_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_9_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
/* Print buffer character limit for prints- UART or CCS Console */
#define APP_PRINT_BUFFER_SIZE (200U)
#define J721E_GPIO_GESI_CAN_STB_PIN (0x003C)
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/* Data length Code(DLC) with respect to Data */
uint32_t gMcanAppdataSize[16] ={
0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64
};
/* CAN TX interrupt flag*/
volatile uint32_t gMcanIsrIntr0Flag = 1U;
/* CAN RX interrupt flag*/
volatile uint32_t gMcan7IsrIntr1Flag = 1U, gMcan9IsrIntr1Flag = 1U;
/* RX interrupt Status*/
volatile uint32_t gRxIntr1Status0 = 0U, gRxIntr1Status1 = 0U;;
/*Hold the CAN instance address */
//uint32_t gMcanModAddr[2];
/* Array of memory base address of CAN instances*/
static uint32_t gMcanMods[] =
{
CSL_MCAN7_MSGMEM_RAM_BASE,
CSL_MCAN9_MSGMEM_RAM_BASE};
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
/* Output pin : CAN STB */
J721E_GPIO_GESI_CAN_STB_PIN | GPIO_CFG_OUTPUT,
};
/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
NULL};
/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config = {
gpioPinConfigs,
gpioCallbackFunctions,
sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
0,
};
/* ========================================================================== */
/* Global Function Declarations */
/* ========================================================================== */
extern Board_STATUS Board_moduleClockEnable(uint32_t moduleId);
/*******************************************************************************
* Function Name : canInstInit
*
* Description : Initialization of CAN parameter
*
* Arguments : None
*
* Return Values : None
*
******************************************************************************/
void canInstInit(uint8_t addressIdx)
{
int32_t configStatus = CSL_PASS;
uint32_t mcanInstAddr;
/* Do Pad Config for MCAN */
padConfig_prcmEnable();
/* MCAN Instance Base address selected */
mcanInstAddr = gMcanMods[addressIdx];
/* CrossBar Configuration */
configStatus = mcanRegisterIsr(mcanInstAddr);
if (CSL_PASS == configStatus)
{
consolePrintf("MCAN Register ISR Done..\n");
}
/* MCAN CAN Bittime, RX TX BUffer/FIFO, Global Filter Configuration */
configStatus = mcanConfig(mcanInstAddr);
if (CSL_PASS == configStatus)
{
consolePrintf("MCAN Configuration Done..\n");
}
/* Select Interrupt Line */
MCAN_selectIntrLine(mcanInstAddr,
MCAN_INTR_MASK_ALL,
MCAN_INTR_LINE_NUM_1);
}
/*******************************************************************************
* Function Name : padConfig_prcmEnable
*
* Description : Pad configuration , Pin Mux configuration
*
* Arguments : None
*
* Return Values : None
******************************************************************************/
void padConfig_prcmEnable()
{
Board_STATUS boardStatus;
/* MCAN 7 Module clocl Enable*/
Board_moduleClockEnable(TISCI_DEV_MCAN7);
/* MCAN 9 Module clocl Enable*/
Board_moduleClockEnable(TISCI_DEV_MCAN9);
/* Pin mux for CAN STB used in GESI board */
*(volatile unsigned int *)(0x0011c0f4) = 0x20007;
/* Pinmux for MAIN_MCAN7 */
*(volatile unsigned int *)(0x0011c074) = 0x60006;
*(volatile unsigned int *)(0x0011c078) = 0x60006;
/* Pinmux for MAIN_MCAN9 */
*(volatile unsigned int *)(0x0011c0cc) = 0x60006;
*(volatile unsigned int *)(0x0011c0d0) = 0x60006;
/* GPIO initialization */
GPIO_init();
appLogPrintf("GPIO_init Done \n");
/* Enable CAN transceivers by setting the STB pins */
/* Enable the TCAN on GESI board.
* Main Domain MCAN instances 4,5,6,7,9,11.
*/
GPIO_write(0, GPIO_PIN_LOW);
}
/*******************************************************************************
* Function Name : mcanConfig
*
* Description : This function will configure MCAN module ,CAN frame format,
* bit time, operation mode, memory config
*
* Arguments : None
*
* Return Values : configuration status
*******************************************************************************/
static int32_t mcanConfig(uint32_t mcanInstAddr)
{
uint32_t fdoe;
int32_t configStatus = CSL_PASS;
MCAN_RevisionId revId;
MCAN_InitParams initParams;
MCAN_ConfigParams configParams;
MCAN_MsgRAMConfigParams msgRAMConfigParams;
MCAN_StdMsgIDFilterElement stdFiltelem;
MCAN_ExtMsgIDFilterElement extFiltelem;
MCAN_BitTimingParams bitTimes;
/* Initialize MCAN Init params */
initParams.fdMode = CAN_FD_OP_ENABLE;
initParams.brsEnable = BAUD_RATE_SWITCH_ENABLE;
initParams.txpEnable = TRANSMIT_PAUSE_DISABLED;
initParams.efbi = EDGE_FILTRING_DISABLED;
initParams.pxhddisable = PROTOCOL_EXCEP_HANDLE_ENABLE;
initParams.darEnable = AUTOMATIC_RETRANSMISSION_DISABLED;
initParams.wkupReqEnable = WAKEUP_REQUEST_ENABLE;
initParams.autoWkupEnable = AUTO_WAKEUP_ENABLE;
initParams.emulationEnable = EMULATION_ENABLE;
initParams.emulationFAck = EMULATION_FAST_ACK_DISABLED;
initParams.clkStopFAck = CLK_STOP_FAST_ACK_DISABLED;
initParams.wdcPreload = START_VAL_MESG_RAM_WATCHDOG_CNTR;
initParams.tdcEnable = TRANS_DELAY_COMPENS_ENABLE;
initParams.tdcConfig.tdcf = TRANS_DELAY_COMPENS_FILTER_WINDOW_LENGTH;
initParams.tdcConfig.tdco = TRANS_DELAY_COMPENS_OFFSET;
/* Initialize MCAN Config params */
configParams.monEnable = BUS_MONITORING_MODE_DISABLED;
configParams.asmEnable = NORMAL_CAN_OPERATION;
configParams.tsPrescalar = TIMESTAMP_CNTR_PRESCALER;
configParams.tsSelect = TIMESTAMP_SOURCE_SELECTTION;
configParams.timeoutSelect = MCAN_TIMEOUT_SELECT_CONT;
configParams.timeoutPreload = START_VAL_TIMEOUT_DOWN_CNTR;
configParams.timeoutCntEnable = TIMEOUT_CNTR_DISABLED;
configParams.filterConfig.rrfs = REJECT_REMOTE_FRAME_STD_ENABLE;
configParams.filterConfig.rrfe = REJECT_REMOTE_FRAME_EXT_ENABLE;
configParams.filterConfig.anfe = REJECT_NONMATCHING_FRAME_EXT;
configParams.filterConfig.anfs = REJECT_NONMATCHING_FRAME_STD;
/* Initialize Message RAM Sections Configuration Parameters */
msgRAMConfigParams.flssa = APP_MCAN_STD_ID_FILT_START_ADDR;
msgRAMConfigParams.lss = APP_MCAN_STD_ID_FILTER_NUM;
msgRAMConfigParams.flesa = APP_MCAN_EXT_ID_FILT_START_ADDR;
msgRAMConfigParams.lse = APP_MCAN_EXT_ID_FILTER_NUM;
msgRAMConfigParams.txStartAddr = APP_MCAN_TX_BUFF_START_ADDR;
msgRAMConfigParams.txBufNum = DEDICATED_TX_BUF_0;
msgRAMConfigParams.txFIFOSize = APP_MCAN_TX_FIFO_SIZE;
msgRAMConfigParams.txBufMode = TX_FIFO_OPERATION;
msgRAMConfigParams.txBufElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
msgRAMConfigParams.txEventFIFOSize = APP_MCAN_TX_BUFF_SIZE;
msgRAMConfigParams.txEventFIFOWaterMark = TX_EVENT_FIFO_WATERMARK_INTR_3;
msgRAMConfigParams.rxFIFO0startAddr = APP_MCAN_FIFO_0_START_ADDR;
msgRAMConfigParams.rxFIFO0size = APP_MCAN_FIFO_0_NUM;
msgRAMConfigParams.rxFIFO0waterMark = RX_EVENT_FIFO_0_WATERMARK_INTR_3;
msgRAMConfigParams.rxFIFO0OpMode = RX_FIFO_0_BLOCKING_MODE;
msgRAMConfigParams.rxFIFO1startAddr = APP_MCAN_FIFO_1_START_ADDR;
msgRAMConfigParams.rxFIFO1size = APP_MCAN_FIFO_1_NUM;
msgRAMConfigParams.rxFIFO1waterMark = RX_EVENT_FIFO_1_WATERMARK_INTR_3;
msgRAMConfigParams.rxFIFO1OpMode = RX_FIFO_1_BLOCKING_MODE;
msgRAMConfigParams.rxBufStartAddr = APP_MCAN_RX_BUFF_START_ADDR;
msgRAMConfigParams.rxBufElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams.rxFIFO0ElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams.rxFIFO1ElemSize = MCAN_ELEM_SIZE_64BYTES;
/* Initialize filter on IDs for incoming CAN frames */
// change in configParams.filterConfig.anfs/anfe for accept/reject non matching frames
/* SFID2 = mask(0) to receive all IDs */
stdFiltelem.sfid2 = SFID2_RECEIVE_ALL_ID_MASK_VAL;
/* SFID1 = filter(0) to receive all IDs */
stdFiltelem.sfid1 = SFID1_RECEIVE_ALL_ID_FILTER_VAL;
/* Store in Rx FIFO 1 if filter matches */
stdFiltelem.sfec = SFEC_STORE_IN_RX_FIFO1;
/* EFID1 = filter, EFID2 = mask */
stdFiltelem.sft = STD_FILTER_TYPE_CLASSIC;
/* EFID2 = mask(0) to receive all IDs */
extFiltelem.efid2 = EFID2_RECEIVE_ALL_ID_MASK_VAL;
/* EFID1 = filter(0) to receive all IDs */
extFiltelem.efid1 = EFID1_RECEIVE_ALL_ID_FILTER_VAL;
/* Store in Rx FIFO 1 if filter matches */
extFiltelem.efec = EFEC_STORE_IN_RX_FIFO1;
/* EFID1 = filter, EFID2 = mask */
extFiltelem.eft = EXT_FILTER_TYPE_CLASSIC;
//500kbps nominal bit rate
bitTimes.nomRatePrescalar = NOMINAL_BR_PRESCALER;
bitTimes.nomTimeSeg1 = NOMINAL_TIMESEG1_BEFORE_SAMPLE_PNT;
bitTimes.nomTimeSeg2 = NOMINAL_TIMESEG2_AFTER_SAMPLE_PNT;
bitTimes.nomSynchJumpWidth = NOMINAL_SYNC_JUMP_WIDTH;
//2Mbps data bit rate
bitTimes.dataRatePrescalar = DATA_BR_PRESCALER;
bitTimes.dataTimeSeg1 = DATA_TIMESEG1_BEFORE_SAMPLE_PNT;
bitTimes.dataTimeSeg2 = DATA_TIMESEG2_AFTER_SAMPLE_PNT;
bitTimes.dataSynchJumpWidth = DATA_SYNC_JUMP_WIDTH;
/* Get MCANSS Revision ID */
MCAN_getRevisionId(mcanInstAddr, &revId);
consolePrintf("gMcanMods:0x%x\n", mcanInstAddr);
consolePrintf("MCANSS Revision ID:\n");
consolePrintf("scheme:0x%x\n", revId.scheme);
consolePrintf("Business Unit:0x%x\n", revId.bu);
consolePrintf("Module ID:0x%x\n", revId.modId);
consolePrintf("RTL Revision:0x%x\n", revId.rtlRev);
consolePrintf("Major Revision:0x%x\n", revId.major);
consolePrintf("Custom Revision:0x%x\n", revId.custom);
consolePrintf("Minor Revision:0x%x\n", revId.minor);
/* Enable Auto wakeup */
fdoe = MCAN_isFDOpEnable(mcanInstAddr);
if ((uint32_t)TRUE == fdoe)
{
consolePrintf("CAN-FD operation is enabled through E-Fuse.\n");
}
else
{
consolePrintf("CAN-FD operation is disabled through E-Fuse.\n");
}
/* wait for memory initialization to happen */
while (FALSE == MCAN_isMemInitDone(mcanInstAddr))
{}
/* Put MCAN in SW initialization mode */
MCAN_setOpMode(mcanInstAddr, MCAN_OPERATION_MODE_SW_INIT);
while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(mcanInstAddr))
{}
/* Initialize MCAN module */
MCAN_init(mcanInstAddr, &initParams);
/* Configure MCAN module */
MCAN_config(mcanInstAddr, &configParams);
/* Configure Bit timings */
MCAN_setBitTime(mcanInstAddr, &bitTimes);
/* Set Extended ID Mask */
MCAN_setExtIDAndMask(mcanInstAddr, APP_MCAN_EXT_ID_AND_MASK);
/* Configure Message RAM Sections */
MCAN_msgRAMConfig(mcanInstAddr, &msgRAMConfigParams);
/* Configure Standard ID filter element */
MCAN_addStdMsgIDFilter(mcanInstAddr, 0U, &stdFiltelem);
/* Configure Extended ID filter element */
MCAN_addExtMsgIDFilter(mcanInstAddr, 0U, &extFiltelem);
/* Take MCAN out of the SW initialization mode */
MCAN_setOpMode(mcanInstAddr, MCAN_OPERATION_MODE_NORMAL);
while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(mcanInstAddr))
{}
return configStatus;
}
/*******************************************************************************
* Function Name : mcanRegisterInterrupt
*
* Description : Enable CPU Interrrupts and Register ISR
*
*
* Arguments : inttrupt vector num, Function address
* void f(uintptr_t) implicitaly converted to void (*f)(uintptr_t)
*
* Return Values : configStatus
******************************************************************************/
static int32_t mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t))
{
int32_t configStatus = STW_SOK;
OsalRegisterIntrParams_t intrPrms;
OsalInterruptRetCode_e osalRetVal;
HwiP_Handle hwiHandle = NULL;
/* Enable CPU Interrupts and register ISR*/
Osal_RegisterInterrupt_initParams(&intrPrms);
/* Populate the interrupt parameters */
intrPrms.corepacConfig.arg = (uintptr_t) NULL;
intrPrms.corepacConfig.isrRoutine = f;
intrPrms.corepacConfig.priority = 0U;
intrPrms.corepacConfig.corepacEventNum = 0U;
intrPrms.corepacConfig.intVecNum = intNum;
/* Register interrupts */
osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
if(OSAL_INT_SUCCESS != osalRetVal)
{
configStatus = CSL_EFAIL;
}
return configStatus;
}
/*******************************************************************************
* Function Name : mcanTSIntrISR
*
* Description : This is Interrupt Service Routine for MCAN TimeStamp interrupt
*
* Arguments : ptr
*
* Return Values : None
******************************************************************************/
static void mcanTSIntrISR(uintptr_t arg)
{
consolePrintf("Time Stamp overflow happened.\n");
}
/*******************************************************************************
* Function Name : mcanRegisterIsr
*
* Description : This API will register MCAN ISR
*
* Arguments : CAN instance(Bus) address
*
* Return Values : Config Status
******************************************************************************/
static int32_t mcanRegisterIsr(uint32_t mcanInstAddr)
{
int32_t configStatus = STW_SOK,configStatus1 = STW_SOK, configStatus2 = STW_SOK;
/* Main MCAN Inst 9 */
if(mcanInstAddr == CSL_MCAN9_MSGMEM_RAM_BASE)
{
consolePrintf("CrossBar/Interrupt Configuration for MCAN9.\n");
configStatus2 = mcanRegisterInterrupt(APP_MAIN_MCAN_9_INT0, &mcanIntr0ISR_tx);
configStatus2 += mcanRegisterInterrupt(APP_MAIN_MCAN_9_INT1, &mcanIntr1ISR_rx);
configStatus2 += mcanRegisterInterrupt(APP_MAIN_MCAN_9_TS_INT, &mcanTSIntrISR);
if (STW_SOK != configStatus2)
{
consolePrintf("CrossBar/Interrupt Configuration failed.\n");
}
else
{
consolePrintf("CrossBar/Interrupt Configuration done.\n");
}
return configStatus2;
}
else if(mcanInstAddr == CSL_MCAN7_MSGMEM_RAM_BASE)
{
/* Main MCAN Inst 9 */
consolePrintf("CrossBar/Interrupt Configuration for MCAN7.\n");
configStatus1 = mcanRegisterInterrupt(APP_MAIN_MCAN_7_INT0, &mcanIntr0ISR_tx);
configStatus1 += mcanRegisterInterrupt(APP_MAIN_MCAN_7_INT1, &mcanIntr1ISR_rx);
configStatus1 += mcanRegisterInterrupt(APP_MAIN_MCAN_7_TS_INT, &mcanTSIntrISR);
if (STW_SOK != configStatus1)
{
consolePrintf("CrossBar/Interrupt Configuration failed.\n");
}
else
{
consolePrintf("CrossBar/Interrupt Configuration done.\n");
}
return configStatus1;
}
return configStatus;
}
/*******************************************************************************
* Function Name : canReceiveMsgs
*
* Description : Read Data from CAN BUS and store into local buffer rxMsg
*
* Arguments : local buffer to store received can frame
*
* Return Values : Status
******************************************************************************/
int32_t canReceiveMsgs(MCAN_RxBufElement *rxMsg, uint8_t addressIdx)
{
static uint32_t rxFifo1Idx0 = 0U,rxFifo1Idx1 = 0U;
int32_t rxProcessStatus = CSL_PASS;
MCAN_RxNewDataStatus newDataStatus;
MCAN_ErrCntStatus errCounter;
MCAN_ProtocolStatus protStatus;
MCAN_RxFIFOStatus fifoStatus0,fifoStatus1;
volatile uint32_t mcanInstAddr0, mcanInstAddr1;
MCAN_HighPriorityMsgInfo hpm;
if(addressIdx == 0)
{
mcanInstAddr0 = gMcanMods[0];
/* Enable Interrupts for RX */
MCAN_enableIntr(mcanInstAddr0, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
MCAN_enableIntr(mcanInstAddr0,
MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
/* Enable Interrupt Line */
MCAN_enableIntrLine(mcanInstAddr0,
MCAN_INTR_LINE_NUM_1,
1U);
}
else
{
mcanInstAddr1 = gMcanMods[1];
/* Enable Interrupts for RX */
MCAN_enableIntr(mcanInstAddr1, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
MCAN_enableIntr(mcanInstAddr1,
MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
/* Enable Interrupt Line */
MCAN_enableIntrLine(mcanInstAddr1,
MCAN_INTR_LINE_NUM_1,
1U);
}
// waiting for interrupt to be cleared by ISR for MCAN9
consolePrintf(" wait for interrupt to be cleared by ISR\n");
while (gMcan7IsrIntr1Flag && gMcan9IsrIntr1Flag)
{}
consolePrintf("gMcan9IsrIntr1Flag..%d\n",gMcan9IsrIntr1Flag);
consolePrintf("gMcan7IsrIntr1Flag..%d\n",gMcan7IsrIntr1Flag);
// if(mcanInstAddr == CSL_MCAN9_MSGMEM_RAM_BASE)
if(gMcan9IsrIntr1Flag == 0)
{
gMcan9IsrIntr1Flag = 1U;
/* Checking for Errors */
MCAN_getErrCounters(mcanInstAddr1, &errCounter);
consolePrintf("MCAN9 Error Counter ..recErrCnt =%d canErrLogCnt =%d\n",errCounter.recErrCnt,errCounter.canErrLogCnt );
MCAN_getHighPriorityMsgStatus(mcanInstAddr1, &hpm);
consolePrintf("MCAN9 MCAN_getHighPriorityMsgStatus ..filterIdx =%d filterList =%d\n",hpm.filterIdx,hpm.filterList );
if ((0U == errCounter.recErrCnt) &&
(0U == errCounter.canErrLogCnt))
{
MCAN_getNewDataStatus(mcanInstAddr1, &newDataStatus);
MCAN_clearNewDataStatus(mcanInstAddr1, &newDataStatus);
fifoStatus1.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
MCAN_getRxFIFOStatus(mcanInstAddr1, &fifoStatus1);
//rxFifo1Idx1 = fifoStatus1.getIdx;
consolePrintf("MCAN9 FIFO index num..%d\n",fifoStatus1.getIdx);
consolePrintf("MCAN9 FIFO fillLvl..%d\n",fifoStatus1.fillLvl);
MCAN_readMsgRam(mcanInstAddr1,
MCAN_MEM_TYPE_FIFO,
fifoStatus1.getIdx,
fifoStatus1.num,
rxMsg);
// read out(drain) message from RXFIFO1
MCAN_writeRxFIFOAck(mcanInstAddr1, fifoStatus1.num, fifoStatus1.getIdx);
MCAN_getProtocolStatus(mcanInstAddr1, &protStatus);
if (MCAN_PSR_BO_BUS_OFF == protStatus.busOffStatus)
{
consolePrintf("MCAN9 BUSOFF Error..\n");
}
// increment FIFO Index to store new message at RXFIFO1[rxFifo1Idx]
consolePrintf("MCAN9 Rx Message Received\n");
}
else
{
consolePrintf("MCAN9 CSL_EFAIL\n");
rxProcessStatus = CSL_EFAIL;
}
}
// if(mcanInstAddr == CSL_MCAN7_MSGMEM_RAM_BASE)
else if(gMcan7IsrIntr1Flag == 0)
{
gMcan7IsrIntr1Flag = 1U;
/* Checking for Errors */
MCAN_getErrCounters(mcanInstAddr0, &errCounter);
consolePrintf("MCAN7 Error Counter ..recErrCnt =%d canErrLogCnt =%d\n",errCounter.recErrCnt,errCounter.canErrLogCnt );
MCAN_getHighPriorityMsgStatus(mcanInstAddr1, &hpm);
consolePrintf("MCAN9 MCAN_getHighPriorityMsgStatus ..filterIdx =%d filterList =%d\n",hpm.filterIdx,hpm.filterList );
if ((0U == errCounter.recErrCnt) &&
(0U == errCounter.canErrLogCnt))
{
MCAN_getNewDataStatus(mcanInstAddr0, &newDataStatus);
MCAN_clearNewDataStatus(mcanInstAddr0, &newDataStatus);
fifoStatus0.num = (uint32_t)MCAN_RX_FIFO_NUM_1;
MCAN_getRxFIFOStatus(mcanInstAddr0, &fifoStatus0);
// rxFifo1Idx0 = fifoStatus0.getIdx;
consolePrintf("MCAN7 FIFO index num..%d\n",fifoStatus0.getIdx);
consolePrintf("MCAN7 FIFO fillLvl..%d\n",fifoStatus0.fillLvl);
MCAN_readMsgRam(mcanInstAddr0,
MCAN_MEM_TYPE_FIFO,
fifoStatus0.getIdx,
fifoStatus0.num,
rxMsg);
// read out(drain) message from RXFIFO1
MCAN_writeRxFIFOAck(mcanInstAddr0, fifoStatus0.num, fifoStatus0.getIdx);
MCAN_getProtocolStatus(mcanInstAddr0, &protStatus);
if (MCAN_PSR_BO_BUS_OFF == protStatus.busOffStatus)
{
consolePrintf("MCAN7 BUSOFF Error..\n");
}
// increment FIFO Index to store new message at RXFIFO1[rxFifo1Idx]
consolePrintf("MCAN7 Rx Message Received\n");
}
else
{
consolePrintf("MCAN7 CSL_EFAIL\n");
rxProcessStatus = CSL_EFAIL;
}
}
return rxProcessStatus;
}
/*******************************************************************************
* Function Name : mcanIntr0ISR_tx
*
* Description : This is Interrupt Service Routine for MCAN interrupt 0
* and is invoked when CAN message transmission is completed
*
* Arguments : Ptr
*
* Return Values : None
******************************************************************************/
static void mcanIntr0ISR_tx(uintptr_t arg)
{
uint32_t intrStatus;
intrStatus = MCAN_getIntrStatus(gMcanMods[0]);
MCAN_clearIntrStatus(gMcanMods[0], intrStatus);
consolePrintf("\nInside MCAN Tx ISR. Intr Status : 0x%x", intrStatus);
if (MCAN_INTR_SRC_TRANS_COMPLETE ==
(intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
{
gMcanIsrIntr0Flag = 0U;
consolePrintf("\nTx flag cleared");
}
}
/*******************************************************************************
* Function Name : mcanIntr1ISR_rx
*
* Description : This is Interrupt Service Routine for MCAN interrupt 1
* and is invoked when CAN message received
*
* Arguments : Ptr
*
* Return Values : None
******************************************************************************/
static void mcanIntr1ISR_rx(uintptr_t arg)
{
gRxIntr1Status0 = MCAN_getIntrStatus(gMcanMods[0]);
MCAN_clearIntrStatus(gMcanMods[0], gRxIntr1Status0);
consolePrintf("MCAN 7 Rx interrupt status= %d\n",gRxIntr1Status0);
if ((MCAN_INTR_SRC_RX_FIFO1_NEW_MSG == (gRxIntr1Status0 & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
|| (MCAN_INTR_SRC_RX_FIFO1_WATERMARK == (gRxIntr1Status0 & MCAN_INTR_SRC_RX_FIFO1_WATERMARK))
|| (MCAN_INTR_SRC_RX_FIFO1_FULL == (gRxIntr1Status0 & MCAN_INTR_SRC_RX_FIFO1_FULL))
|| (MCAN_INTR_SRC_RX_FIFO1_MSG_LOST == (gRxIntr1Status0 & MCAN_INTR_SRC_RX_FIFO1_MSG_LOST)))
{
consolePrintf("Rx MCAN7 interrupt flag cleared\n");
gMcan7IsrIntr1Flag = 0U;
}
gRxIntr1Status1 = MCAN_getIntrStatus(gMcanMods[1]);
MCAN_clearIntrStatus(gMcanMods[1], gRxIntr1Status1);
consolePrintf("MCAN 9 Rx interrupt status= %d\n",gRxIntr1Status1);
if ((MCAN_INTR_SRC_RX_FIFO1_NEW_MSG == (gRxIntr1Status1 & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
|| (MCAN_INTR_SRC_RX_FIFO1_WATERMARK == (gRxIntr1Status1 & MCAN_INTR_SRC_RX_FIFO1_WATERMARK))
|| (MCAN_INTR_SRC_RX_FIFO1_FULL == (gRxIntr1Status1 & MCAN_INTR_SRC_RX_FIFO1_FULL))
|| (MCAN_INTR_SRC_RX_FIFO1_MSG_LOST == (gRxIntr1Status1 & MCAN_INTR_SRC_RX_FIFO1_MSG_LOST)))
{
consolePrintf("Rx MCAN9 interrupt flag cleared\n");
gMcan9IsrIntr1Flag = 0U;
}
}
/*******************************************************************************
* Function Name : consolePrintf
*
* Description : This is function for printing data on console.
*
* Arguments : String
*
*****************************************************************************/
void consolePrintf(const char *pcString, ...)
{
static char printBuffer[APP_PRINT_BUFFER_SIZE];
va_list arguments;
/* Start the varargs processing. */
va_start(arguments, pcString);
vsnprintf(printBuffer, sizeof(printBuffer), pcString, arguments);
printf(printBuffer);
/* End the varargs processing. */
va_end(arguments);
}
/*******************************************************************************
* Function Name : mcanPrintRxMsg
*
* Description : This is function for printing Rx data on console.
*
* Arguments : Rx CAN buffer
*
* Return Values : None
******************************************************************************/
void mcanPrintRxMsg(const MCAN_RxBufElement *rxMsg)
{
uint32_t loopCnt;
consolePrintf("\nMessage ID(hex): 0x%x", rxMsg->id);
consolePrintf("\nMessage Remote Transmission Request: 0x%x", rxMsg->rtr);
consolePrintf("\nMessage Extended Frame ID(0:11Bit ID/1:29bit ID): 0x%x",
rxMsg->xtd);
consolePrintf("\nMessage Error State Indicator(0:Error Active/1:Error Passive): 0x%x",
rxMsg->esi);
consolePrintf("\nMessage TimeStamp: 0x%x", rxMsg->rxts);
consolePrintf("\nMessage Data Length Code: 0x%x", rxMsg->dlc);
consolePrintf("\nMessage BRS: 0x%x", rxMsg->brs);
consolePrintf("\nMessage CAN FD format: 0x%x", rxMsg->fdf);
consolePrintf("\nMessage Filter Index: 0x%x", rxMsg->fidx);
consolePrintf("\nMessage Accept Non-matching Frame: 0x%x", rxMsg->anmf);
for (loopCnt = 0U; loopCnt < gMcanAppdataSize[rxMsg->dlc]; loopCnt++)
{
consolePrintf("\nMessage DataByte%d", loopCnt);
consolePrintf(": 0x%x", rxMsg->data[loopCnt]);
}
}
