• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 99 subscribers
  • Views 475 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678: Cannot Access DDR3 EMIF Configuration Space via PCIE - Getting PCIE Completer Abort Error

Joseph Furno
Intellectual 300 points
Part Number: TMS320C6678

We are using the TMDSEVM6678LE EVM board are trying to boot via PCIE boot mode.

We have modified the IBL to remove the PLL and PCIE "Work-Arounds" since our board has Rev 2.0 of Silicon and we need to change the PCIE BAR Window Sizes.

When trying to perform a PCIE access to the DDR3 EMIF configuration register space, it is failing with a PCIE "Completer Abort" error.

We have configured our PCIE BAR Window Sizes to "BAR Config" 0b1111 so we have 2GB 64 bit Addressing for BAR2/3 and BAR4/5 per Table 2-10 in the TRM.

I have also enabled the Supervisory Mode bit (MST_PRIV) in the Transaction Priority Register.... and verified Bit 16 is set...

KICK0 and KICK1 Chip-Level Registers are also correctly "Un-Locked" and we can access the Chip-Level Register space without an issue and works fine.

Also the Inbound ATT is set to Match BAR 4 with the correct BAR settings and 0x00000000 offset  (also tried direct offset to 0x21000000 and that fails also).

PCIE Transfer to DDR3 EMIF Config Example that's Failing:  (trying to access PHYC Register)

48_A10000E4 -> DSP EVM  Fails with Completer Abort Error

48_80000000 is BAR 4/5 Base Address

00_21000000 is DDR3 EMIF Config Space Base Address

00_000000E4 is PHYC Register Offset

So the PCIE Address of 48_A10000E4 appears correct and is trying to access the DDR3 EMIF Config space accordingly after Inbound Translation but failing.

Can you help us understand why accessing the DDR EMIF Config region is not working and what other steps need to be done for us to gain access to the DDR EMIF Config region.

For our customized board, we are planning to boot directly from PCIE "without" an IBL and need to configure the PCIE, Chip-Level, and DDR EMIF Config accordingly before we can download code to DDR and run.

This is holding-up our development so can you please provide some feedback and direction accordingly.....

Thanks

  • 0
    TI__Expert 4314 points

    Hi Joseph,

    I am not really good with PCIe Boot. But I can direct you to PCIe boot examples in SDK. They are located in  "{TI_RTOS_SDK_FOLDER}\ti\pdk_c667x_2_0_16\packages\ti\boot\examples\pcie"

    Kindly look into the examples and this might solve your issue.

    Thanks,

    Rajarajan U

  • 0 in reply to Rajarajan Uthayakumar
    Intellectual 300 points

    I have looked into several file located in the directory below and nothing has been found so far to address the issue.   

    The directory and files are likely different based on the version of CCS we are using....

    It feels like either there is a power domain issue with the DDR3 EMIF Config block or clocking issue / PLL (DDR PLL) problem.

    Can you provide any details on these dependencies / required setup of these components.

     

    ...\TI\pdk_C6678_1_1_2_5\packages\ti\drv\pcie\example\sample 

  • 0 in reply to Joseph Furno
    TI__Expert 4314 points

    Hi Joseph,

    Joseph Furno said:
    It feels like either there is a power domain issue with the DDR3 EMIF Config block or clocking issue / PLL (DDR PLL) problem.

    For this issue, could you please load and run the GEL file from "Target configuration" in CCS. This is to check all peripherals in EVM are working fine.

    Also refer to this FAQ, https://e2e.ti.com/f/1/t/1062584

    Rajarajan Uthayakumar said:

    I am not really good with PCIe Boot. But I can direct you to PCIe boot examples in SDK. They are located in  "{TI_RTOS_SDK_FOLDER}\ti\pdk_c667x_2_0_16\packages\ti\boot\examples\pcie"

    I have been running these examples on the following version 

    • TI-RTOS SDK: 06.03
    • PDK: 2.0.16
    • CCS: 9.3.0

    The above-mentioned SDK is the latest stable version where many examples in SDK were checked and verified and we do recommend this version to our customers, Kindly give it try.

    Thanks,

    Rajarajan U

  • 0 in reply to Rajarajan Uthayakumar
    TI__Mastermind 22391 points

    can you connect with CCS and see if you can read some of the DDR3 config registers. Make sure that the gel files dont run. That way it does not config the ddr3 registers again. If you can't read the ddr3 config register then it sounds like the clock is disabled to the ddr3 block. 

  • 0
    Intellectual 300 points

    I am now able to access the C6678 DDR3 EMIF Config space.

    Looking into the MSMC Configuration Block, its SES MPAX component allows 32bit to 36bit translations for “Non-CorePac” / Master accesses (PCIe, EDMA….) into the DDR3  EMIF Configuration space.  This was significantly different than the C6657 design, based on their documented address map layout…. For the C6678, it has the same Logical Address but different Physical Address which is in 36bit space at 1_00000000.

    Anyway, I configured the MSMC SES MPAX component through the proper “Un-Lock” mechanism and then configured “ALL” Privilege Table “Pair 1’s” for translation, to bias on the side of caution / success…. and then “Locked” the component appropriately once loaded.

    Note: the C6678 is defaulting “ALL” SES Privilege Tables “Pair 0’s” with translations for the 2GB DDR space.

    Here is a code snip-it of what I did to configure the MSMC SES component and to gain access into the DDR3 EMIF register space.

    MSMC SES MPAX Setup:
    ====================

    MSMCConfigRegisterRead(MSMC_CONFIG_BASE_REG + MSMC_PERIPH_ID, &val);
    xfc_printf("EP PCIE MSMC Peripheral ID = 0x%08X \n", val);

    MSMCConfigRegisterWrite(MSMC_CONFIG_BASE_REG + SES_MPAX_ULCK, SES_MPAX_LOCK_UNLOCK);

    for (i = 0; i < SES_MPAX_NUM_PRIVS; i++)
    {
        MSMCConfigRegisterWrite(MSMC_CONFIG_BASE_REG + SES_MPAXL_0_1 + (i * SES_MPAX_PRIV_OFFSET), 0x100000FF); // Replacement Address + All Permissions
        MSMCConfigRegisterWrite(MSMC_CONFIG_BASE_REG + SES_MPAXH_0_1 + (i * SES_MPAX_PRIV_OFFSET), 0x2100000B); // Base Address + 4 KB Segment Size
    }

    MSMCConfigRegisterWrite(MSMC_CONFIG_BASE_REG + SES_MPAX_LCK, SES_MPAX_LOCK_UNLOCK);