Part Number: TDA4VM
Dear TI Team
Is it possible to share the example shows -how to use "tidl_denylist" option in TIDLCompiler function of test_tidl_j7.py module.
Will there be any difference in the generated deliverable/artifacts when SW is compiled with and without configuration of tidl_denylist. if yes, which module in generated artifiacts depicts the changes ?
Kindly share the detail steps/procedure to infer the TVM compiled model on target(j7-EVM) using TVM inference approch
Note
Versions used :-
SDK: ti-processor-sdk-rtos-j721e-evm-07_01_00_11
TVM version: REL.TIDL.J7.01.03.00.11
OS : Ubuntu 18.04
Thanks :-)