• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 321 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C5504: Clock frequency tolerance

ArTzy
Genius 17385 points
Part Number: TMS320C5504

Hi Experts,

Good day. Seeking assistance on this query:

The "10" grade of the "TMS320C5504AZCH" has a spec of a core voltage of 1.3V and a maximum clock speed of 100MHz, but is it possible to run at a maximum 100MHz clock speed?

For example, is there a recommendation to keep it below 95% etc.? Even if 100MHz clock operation is not a problem, the frequency of the primary oscillator connected to the external of DSP IC also has a tolerance, so even if the internal PLL uprates the frequency to 100MHz, the tolerance will still have an effect.

Please let us know the allowable tolerance of 100MHz clock. Thank you.

Regards,
Archie A.

  • 0
    TI__Intellectual 2695 points

    Hello Archie,

    There is no allowable tolerance provided for the clock speed in the data sheet. The table 5-3 shows the PLL clock frequency ranges at different voltage rail ranges and PLL out has range of upto 120MHz at 1.3V.

    Thank you,

    Anita

  • 0 in reply to Anita Pratti
    TI__Genius 17385 points

    Hi Anita,

    Thanks for your response.

    As to the relation of PLL and SYSCLK for TMS320C5504AZCH10, we'd like to clarify again. At the CVdd=1.3V and Vdda_pll=1.3V, maximum of PLLOUT is 120MHz and SYSCLK is 100MHz, isn't it? If so, our question really is:

    Is SYSCLK possible to run at a maximum 100MHz system clock speed actually? For example, is there a recommendation to keep it below 95% etc.?
    Even if 100MHz system clock operation is not a problem theoretically, the frequency of the primary oscillator connected to the external of DSP IC also has a tolerance.

    Please let us know the allowable tolerance of 100MHz system clock.

    Thank you very much.

    Regards,
    Archie A.

  • +1 in reply to ArTzy
    TI__Intellectual 2695 points

    Hi Archie,

    Our datasheet max frequency for SYSCLK is 100MHZ and it is possible to run upto this max clock frequency without any issues.

    There is no need to keep it below 95% as our testing is done at the max clock frequency and is expected to work at 100MHz without any issues.

    Best regards,

    Anita