Hi,
Recently, we found that the debugger could not stop the CPU while it was waiting for the pcie bus to respond. Is there a way to configure the bus response priority to ensure that debug commands are correctly responded to by the CPU whenever possible.
What is described in Chapter 3 of the chip manual(System Interconnect) seems relevant to what we need. If the configuration described here can meet our needs, can you provide an example of the configuration for our reference?
Thanks.