Problem booting Linux on AM3517

Hi,

I managed to get the kernel boot log by enabling “earlyprintk”. I found a problem in the GPMC configuration. I previously changed the NAND_BASE address to 0x00000000 in U-Boot and X-loader which the kernel didn’t like so I changed it back to 0x30000000.

Now the kernel boots all the way to the point where the filesystem is mounted, but as I at the moment don’t have a filesystem this will fail, which is okay.

But I can also see more errors in the boot log:

[    0.000000] Clocking rate (Crystal/Core/MPU): 26.0/332/500 MHz
[    0.000000] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
[    0.000000] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
[    0.000000] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
[    0.000000] Reprogramming SDRC clock to 332000000 Hz
[    0.000000] dpll3_m2_clk rate change failed: -22
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts
[    0.000000] Total of 96 interrupts on 1 active controller
[    0.000000] GPMC revision 5.0

and

[    0.000000] regulator: core version 0.5
[    0.000000] regulator: dummy:
[    0.000000] NET: Registered protocol family 16
[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: at arch/arm/mach-omap2/pm.c:94 _init_omap_device+0x80/0xa0()
[    0.000000] _init_omap_device: could not find omap_hwmod for iva
[    0.000000] Modules linked in:
[    0.000000] [<c004a51c>] (unwind_backtrace+0x0/0xf0) from [<c0070508>] (warn_slowpath_common+0x4c/0x64)
[    0.000000] [<c0070508>] (warn_slowpath_common+0x4c/0x64) from [<c00705a0>] (warn_slowpath_fmt+0x2c/0x3c)
[    0.000000] [<c00705a0>] (warn_slowpath_fmt+0x2c/0x3c) from [<c0051b30>] (_init_omap_device+0x80/0xa0)
[    0.000000] [<c0051b30>] (_init_omap_device+0x80/0xa0) from [<c001032c>] (omap2_common_pm_init+0x2c/0x10c)
[    0.000000] [<c001032c>] (omap2_common_pm_init+0x2c/0x10c) from [<c003a3b4>] (do_one_initcall+0xcc/0x1a4)
[    0.000000] [<c003a3b4>] (do_one_initcall+0xcc/0x1a4) from [<c000868c>] (kernel_init+0x98/0x14c)
[    0.000000] [<c000868c>] (kernel_init+0x98/0x14c) from [<c0045790>] (kernel_thread_exit+0x0/0x8)
[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[    0.000000] OMAP GPIO hardware version 2.5

Any ideas?

Regards,
Anders

Can you apply this patch and check if you notice the same issue again:

http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap-2.6.git;a=commitdiff;h=2de0baefaa7f2fad221bba6049e389e39990e2f0

Hi,

The changes performed by the patch are already included in the source from AM35x-OMAP35x-PSP 04.02.00.07.

static void omap2_init_processor_devices(void)
{
    _init_omap_device("mpu", &mpu_dev);

    if (omap3_has_iva())
        _init_omap_device("iva", &iva_dev);

    if (cpu_is_omap44xx()) {
        _init_omap_device("l3_main_1", &l3_dev);
        _init_omap_device("dsp", &dsp_dev);

Regards,
Anders

Can you share top 10 lines of the kernel boot log?

I don't have AM3517 with me now, but I am looking for a line similar to following (on DM37x EVM):

OMAP3630/DM3730 ES1.0 (l2cache iva sgx neon isp 192mhz_clk )

This is the top lines of the Kernel boot log that I get when booting:

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
[    0.000000] Linux version 2.6.37 (andga@ubuntu6) (gcc version 4.4.5 (Buildroot 2011.02) ) #20 Mon May 16 12:57:30 CEST 2011
[    0.000000] CPU: ARMv7 Processor [411fc087] revision 7 (ARMv7), cr=10c53c7f
[    0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
[    0.000000] Machine: AM3517 R5CDUP1
[    0.000000] bootconsole [earlycon0] enabled
[    0.000000] Reserving 4194304 bytes SDRAM for VRAM
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] AM3517 ES1.1 (l2cache iva sgx neon isp )
[    0.000000] SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: 0x10000
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 64000
[    0.000000] Kernel command line: mem=256M console=ttyO2,115200n8 root=/dev/ram0 rw initrd=0x83000000,40M ramdisk_size=884736 earlyprintk
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Memory: 252MB = 252MB total
[    0.000000] Memory: 201980k/201980k available, 60164k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
[    0.000000]     vmalloc : 0xd0800000 - 0xf8000000   ( 632 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .init : 0xc0008000 - 0xc0039000   ( 196 kB)
[    0.000000]       .text : 0xc0039000 - 0xc053d384   (5137 kB)
[    0.000000]       .data : 0xc053e000 - 0xc06ebca0   (1720 kB)
[    0.000000] NR_IRQS:375
[    0.000000] Clocking rate (Crystal/Core/MPU): 26.0/332/500 MHz
[    0.000000] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
[    0.000000] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
[    0.000000] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
[    0.000000] Reprogramming SDRC clock to 332000000 Hz
[    0.000000] dpll3_m2_clk rate change failed: -22
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts
[    0.000000] Total of 96 interrupts on 1 active controller
[    0.000000] GPMC revision 5.0

For the time being you should be able to get rid of this error by removing / commenting these lines:

    if (omap3_has_iva())
        _init_omap_device("iva", &iva_dev);

Let me know the outcome ... until I am able to gather more info.

Yes this removed the iva error message.

Do you know anything about the other errors, the softreset, and the dpll3_m2_clk rate change:

[    0.000000] Clocking rate (Crystal/Core/MPU): 26.0/332/500 MHz
[    0.000000] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
[    0.000000] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
[    0.000000] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
[    0.000000] Reprogramming SDRC clock to 332000000 Hz
[    0.000000] dpll3_m2_clk rate change failed: -22
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts

I believe you can ignore the soft reset errors. The HWMOD layer attempts to reset the I2C by writing to the SYSCONFIG register with may not be right thing to do. Functionally, it doesn't cause any problems. These errors were discussed earlier in the year - though I don;t remember if the solution was accepted. Will try to get more details tomorrow...

You mentioned in the first post that you are using a custom board. What is the memory part on the board?

Return value -22 indicates -EINVAL most likely there is a failure while trying to reprogram the SDRC. The system will still continue to work based on the settings done in u-boot. Will be able to share more details tomorrow.

Regarding I2C soft reset:
  You can follow the current discussion on this issue here:
  http://marc.info/?t=130432829700001&r=1&w=2
  The patch describes issue in detail:
  http://marc.info/?l=linux-omap&m=130432819300534&w=2

Regarding -22 return value:
  Can you apply this patch and see whether it helps:
  http://marc.info/?l=linux-arm-kernel&m=130494422504941&w=2

I am using two Micron MT47H64M16HR-3 DDR2 memory’s. I have changed the configurations in X-loader and u-boot.
I thought that Linux would use the settings made by u-boot, but maybe this is not the case.

Will Linux try to setup the SDRC for itself?
Then I need to find and change the setup in Linux also.

Linux doesn't change the SDRC setup unless there is a change in frequency; but it must follow the clock hierarchy to take stock of all the clocks.

Did the patches I referred in earlier post help? (PS: I don't have the board for me to try things. Anyway doing things by yourself will help you get better acquainted with the code.)

Hi

The patch for the -22 return value, didn’t remove the error message. But I have done some more investigation and found the problem.

The omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) function referred to in the patch fails on the omap2_sdrc_get_params() as there are no SDRC register values configured for the board.

The SDRC register values are given in a struct for different clock rates and configured in the board file using the omap2_init_common_devices(sdrc_cs0, sdrc_cs1). But in the board file this is set to “NULL” (omap2_init_common_devices(NULL, NULL)). This is also true for the AM3517 EVM board file, so the error should also be visible on the AM3517 EVM setup. To remove the error I need to supply my own setup for the MT47H64M16HR-3.

The patch for the i2c didn’t remove the error it only change the function called for I2C soft reset but the new function returns the same error message. I haven’t had the time to investigate this closer yet.

[    0.000000] omap_i2c_reset: i2c1: softreset failed (waited 10000 usec)
[    0.000000] omap_i2c_reset: i2c2: softreset failed (waited 10000 usec)
[    0.000000] omap_i2c_reset: i2c3: softreset failed (waited 10000 usec)
[    0.000000] Reprogramming SDRC clock to 332000000 Hz

I'm using the AM3505 with Micron MT47H128M16 SDRAM and I'm observing the 'dpll3_m2_clk rate change failed: -22' message.  Can someone point me to the documentation for computing the struct omap_sdrc_params values to setup the part and remove the error?

Thanks,
...doug

I found the information I was looking for here:

http://processors.wiki.ti.com/index.php/Setting_up_OMAP35x_SDRC_registers

...doug