Hi,
I want to connect 2 aic33 codec with 5509A through a signal MCBSP , but I alway failed, the data that I collect from aic33 seems alway noise, from the document of TI I see that, I need to configure MCBSP into TDM mode. so I want to know if some of you know how to configure it?
By now I set the MCBSP and AIC33 working in DSP mode and FRLEN = 3, WDLEN=16bit, I have attached my code, really hope you can help me to check it, thank you very much :-)
MCBSP_Config Mcbsp0Config = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF, // DLB = 0
MCBSP_SPCR1_RJUST_LZF, // RJUST = 0,right justify the data and zero fill the MSBs
MCBSP_SPCR1_CLKSTP_DISABLE, // CLKSTP = 0
MCBSP_SPCR1_DXENA_ON, // DXENA = 1,DX delay enabler on
0, // Reserved = 0
MCBSP_SPCR1_RINTM_RRDY, // RINTM = 0
MCBSP_SPCR1_RSYNCERR_NO, // RSYNCER = 0
MCBSP_SPCR1_RRST_DISABLE // RRST = 0; Disable receiver
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO, // FREE = 0
MCBSP_SPCR2_SOFT_NO, // SOFT = 0
MCBSP_SPCR2_FRST_FSG, // FRST = 1 ; Enable the frame-sync logic
MCBSP_SPCR2_GRST_CLKG, // GRST = 1 ; The sample rate generator is take out of its reset state
MCBSP_SPCR2_XINTM_XRDY, // XINTM = 0
MCBSP_SPCR2_XSYNCERR_NO, // XSYNCER =0
MCBSP_SPCR2_XRST_DISABLE // XRST = 0 Disable transimitter
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(3), // RFRLEN1 = 1
MCBSP_RCR1_RWDLEN1_16BIT // RWDLEN1 = 2 ----->32bit<---------
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, // RPHASE = 0
MCBSP_RCR2_RFRLEN2_OF(0), // RFRLEN2 = 0
MCBSP_RCR2_RWDLEN2_8BIT, // RWDLEN2 = 0
MCBSP_RCR2_RCOMPAND_MSB, // RCOMPAND = 0 No companding,any size data, MSB received first
MCBSP_RCR2_RFIG_YES, // RFIG = 1 Frame-sync ignore
MCBSP_RCR2_RDATDLY_1BIT // RDATDLY = 1 1-bit data delay
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(3), // XFRLEN1 = 1
MCBSP_XCR1_XWDLEN1_16BIT // XWDLEN1 = 2 ----->32bit<---------
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, // XPHASE = 0
MCBSP_XCR2_XFRLEN2_OF(0), // XFRLEN2 = 0
MCBSP_XCR2_XWDLEN2_8BIT, // XWDLEN2 = 0
MCBSP_XCR2_XCOMPAND_MSB, // XCOMPAND = 0
MCBSP_XCR2_XFIG_YES, // XFIG = 1 Unexpected Frame-sync ignore
MCBSP_XCR2_XDATDLY_1BIT // XDATDLY = 1 1-bit data delay
),
/*MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0), // XPHASE = 0
MCBSP_SRGR1_CLKGDV_OF(0) // XFRLEN2 = 0
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE, // XPHASE = 0
MCBSP_SRGR2_CLKSP_RISING, // XFRLEN2 = 0
MCBSP_SRGR2_CLKSM_INTERNAL, // XWDLEN2 = 0
MCBSP_SRGR2_FSGM_FSG, // XCOMPAND = 0
MCBSP_SRGR2_FPER_OF(31) // XDATDLY = 1 1-bit data delay
), */
MCBSP_SRGR1_DEFAULT,
MCBSP_SRGR2_DEFAULT,
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_RESET, // IDLEEN = 0
MCBSP_PCR_XIOEN_SP, // XIOEN = 0
MCBSP_PCR_RIOEN_SP, // RIOEN = 0
MCBSP_PCR_FSXM_EXTERNAL, // FSXM = 0 Tranmit frame-syn is provided by AIC23B
MCBSP_PCR_FSRM_EXTERNAL, // FSRM = 0 Receive frame-syn is provided by AIC23B
MCBSP_PCR_CLKXM_INPUT, // CLKR is input
MCBSP_PCR_CLKRM_INPUT, // CLKX is input
MCBSP_PCR_SCLKME_NO, // SCLKME=0 CLKG is taken from the McBSP internal input clock
// MCBSP_PCR_CLKSSTAT_0, // The signal on the CLKS pin is low
MCBSP_PCR_DXSTAT_0, // Drive the signal on the DX pin low
// MCBSP_PCR_DRSTAT_0, // The signal on the DR pin is low
MCBSP_PCR_FSXP_ACTIVEHIGH, // FSXP = 1 Because a falling edge on LRCIN or LRCOUT starts data transfer
MCBSP_PCR_FSRP_ACTIVELOW, // FSRP = 1
MCBSP_PCR_CLKXP_FALLING, // CLKXP = 1 The falling edge of BCLK starts data transfer
MCBSP_PCR_CLKRP_RISING // CLKRP = 1
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};