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EMIFA: Accessing Larger Asynchronous Memories

Francesco Danilo De Vita
Intellectual 255 points

Hi.

In the sprufl6e (EMIFA User's guide) it is reported the phrase "then GPIO pins may be used to control the flash device’s upper address lines".

My question is: how does the processor combine EMIF Address lines with these GPIO pins? Can We use every GPIO pins?

What do we have to set beyond the PINMUX registers for these pins?

De Vita F. Danilo

  • 0
    TI__Genius 9490 points

    Francesco,

    Essentially you would need to bit bang the GPIOs to mimic the page addressing etc. There is no 'emif mode' for the GPIO peripheral.  Any GPIO pin available that is not being used can essentially be used for this purpose.  The GPIO pins do not become an actual part of the EMIFA. The GPIO pins are always controlled by direct register writes from the CPU. This means that anytime the EMIFA reaches an address boundary (determined by the number of EMIFA address pins available) the CPU must flip a GPIO pin to change the 'page' of the ASYNC device.  This schema is typically used in other processors where the AEMIF contained only a limited set of addres lines, for example if only 13 address lines are avilable, as a result, any address accesses beyond 2^13 have to be controlled by manually toggling a GPIO pin.

    hope this helps,

    regards,

    miguel


  • 0 in reply to Miguel A. Alanis
    Intellectual 255 points

    Ok, thank you, Miguel for your fast answer.

    The concept, now, is quite clear, but I have some concern yet.

    Must GPIOs, selected to make this paging mechanism, be connected in ascending order?
    Must first address lines, uncovered by EMA_A pin, be connected with the first not used GPIO?

    For example:
    A[15] and A[16] of the asyncronous memory are uncovered by EMA_A pin.
    I have GPIO0_7, GPIO0_8, GPIO0_9 pin not used.

    Which pin configuration must I use?

    This is the only possible configuration:
    A[15] -> GPIO0_7
    A[16] -> GPIO0_8

    or I can connect in this way:
    A[15] -> GPIO0_9
    A[16] -> GPIO0_8
    GPIO0_7 not connected.

    In the second case, how the processor know that must toggle first the GPIO0_8 and than GPIO_09?

     

    Danilo

     

  • 0 in reply to Francesco Danilo De Vita
    TI__Genius 9490 points

    Danilo,

    No they don't have to be connected in Ascending order.

    Your code should be able to handle the toggling of the specific GPIO that you are using to toggle to access the specific Address bit when needed.

    regards,

    miguel