This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

VPSS / FBDEV Usage



Question on the VPPSS/FBDEV interface.  In our design we have connected an LCD display to  VOUTO and plan to drive it using RGB88 mode.  Looking at the documentation for the vpss driver it is not clear to me how to map the output /dev/fb0 to this output. Is this configured through display0 on the driver? 

 /sys/devices/platform/display0

 Do I need to switch the graphic output to this display?

 echo 1:hdmi > /sys/devices/platform/vpss/graphics0/nodes

 It is not clear to me if VOUT0 and the hdmi output are mutually exclusive.

 

Thanks,

 Craig

  • Craig

    VOUT0 is DVO2(display1).

    The following command will connect the fb0 output to VOUT0.

    echo 1:dvo2 > /sys/devices/platform/vpss/graphics/nodes

    Regards,

    yihe

  • yihe,

     Thanks for the answer above.  This does indeed seem to work.  So a follow up question. 

     We have set an LCD VOUT0 display off up display1 to be 800x480 RGB888 and the correct timing for the display. 

     When I open up fbo and use the IOCTL command   FBIOGET_FSCREENINFO it lists the screen resolution has 1280x720 with 32 bits per pixel.  Do I also need to configure fbo using IOCTL commands to match the device screen resolution of the device or are these independent?

     

    Craig

  • Craig,

    Yes, please use FBIOPUT_VSCREENINFO IOCTl to set the proper xres/yres/xres_virtual/yres_virtual, bpp and other stuffs. There is a fbdev example code inside the PSP package. You can refer that file

    Regards,

     

    yihe

  • yihe,

     

    Just so I am clear.  We not only have to setup the resolution and timing for Display1, but also we have to setup the frame buffer to match.  We are doing the following to drive our LCD display.

     -- Connect fbo to display1 to drive VOUTO

    echo 1:dvo2 > /sys/devices/platform/vpss/graphics0/nodes

     -- Setup the timing correct for our display

    echo 148500,1920/88/148/44,1080/4/36/5,1 > /sys/devices/platform/vpss/display1/timings

     -- Setup the correct mode for the output

    echo single,rgb888 > /sys/devices/platform/vpss/display1/output

     -- Then run using the IOCTL FBIOPUT_VSCREENINFO we would setup the correct:

    - Screen resolution (800x480), bpp, Pixel clk, etc..

     Not sure if I understand why we need to setup display1 and the FBO? 

     

    Thanks for the help/explanation

     

    Craig

     

  • Hi,

    I think you are confused with Vout0 and on-chip HDMI. Here is the mapping for the Vout and encoders.

     

    Vout[0] --> DVO2 encoder.

    Vout[1] --> on-chip HDMI encoder.

    So if you are trying to us DVO2 that is named as display1 under the linux sysfs and you should set timings on that. If you are trying on-chip HDMI of Vout[1] you should use display0 for set timings. Hope this clears the confusion. By default graphics 0 is connected to onchip HDMI (Vout[1]).

     

    Regards,

    Hardik Shah

  • Craig,

    Do you want to have 1920x1080P60 resolution or 800x480 resolution?

    1. if you want to have 1920x1080P60, you do not need the following since by default DVO2(VOUT0/Display1) is set to 1080P60.

    • no need to do this: echo 148500,1920/88/148/44,1080/4/36/5,1 > /sys/devices/platform/vpss/display1/timings

    • IOCTL FBIOPUT_VSCREENINFO to set proper parameter

    2. if you want to have 800x480 resolution,

    •   set the propoer timing parameter through /sys/devices/platform/vpss/display1/timings
    • IOCTL FBIOPUT_VSCREENINFO to set proper paramter

    Regards,

    yihe

  • Yihe,

     

    Thanks for the response.  I have been out of  town, so just getting back to this.  We are using a LCD display at 800x480 (Nec - NL8048BC19 with a FIN3885 bus driver between the integra and the display).  We are having issues getting any thing to show up on the LCD display.  We believe we have the timing for the display setup correctly, but don't see any data.  We are using the sysclass interface to configure the display and  are doing the following commands:

     

    //

    // Setup Timing

    //

    echo 0 > /sys/devices/platform/vpss/graphics0/enabled

    echo 0 > /sys/devices/platform/vpss/display1/enabled

    echo 32256,800/112/112/1,480/20/25/1,1 > /sys/devices/platform/vpss/display1/timings

    echo 1 > /sys/devices/platform/vpss/display1/enabled

    echo 1 > /sys/devices/platform/vpss/graphics0/enabled

    //

    //  Change the mode to RGB 888

    //

    echo 0 > /sys/devices/platform/vpss/display1/enabled

    echo single,rgb888 > /sys/devices/platform/vpss/display1/output

    echo 1 > /sys/devices/platform/vpss/display1/enabled

     

    //

    //  Switch the node

    //

    echo 0 > /sys/devices/platform/vpss/graphics0/enabled

    echo 1:dvo2 > /sys/devices/platform/vpss/graphics0/nodes

    echo 1 > /sys/devices/platform/vpss/graphics0/enabled

     

     

    We are also setting up FB0 to be the correct resolution for the display (800x480) and bits per pixel to 24.  So a few questions:


    1. We are not sure what sync mode  to use for the RGB (single/double/doublediscrete/triple/triplediscrete).  Can you shed some light on what each of these sync modes are or point us to where they are defined?

    1. Do we need to configure more settings in the FB0 to match our display?

     

    1. Is there anything else you can point us to look at to further try and isolate where the issue may be?

     

     

    Thanks,

    Craig

  • Craig,

    based on the timing information you provide, the pixel clock should be 32349KHz = (800 + 112 + 112 + 1) * (480 + 20 + 25 + 1) * 60.

    "single" sync mode is not the option for you.  First could you answer the following questions:

    1. Does Panel take embedded sync or discrete sync?

    2. Does panel support RGB24 bit or YUV422 16 bit format

    these two answers will deside how to configure the /sys/devices/platform/vpss/display1/output based on the followings.

    double-> 16 bit YUV422 with embedded sync, doublediscrete: 16-bit YUV422 discrete sync, triple: 24bit RGB888 embedded sync: triplediscrete:24bit RGB888 discrete sync.

    Moreover, current Driver does not have sysfs entry to configure the polariry of the following signal:

    field id, vertical sync, horizontal sync and active video.

    polarity fo these signal are fixed to "ACTIVE HIGH", please check your panel to make sure this.

    I assume that the backlight and power of the pannel was setup correctly in your system.

    Regards,

    yihe

  • Yihe,

    1)      The panel takes a discrete data enable single (DE).   We are using the VOUT[0]_AVID signal for this purpose.  I have attached the LCD display specification for reference.

    2)      The panel takes a RGB24 bit signal

    3)      We believe the backlight and power for the LCD is setup correctly. 

    4)      Per your response, is seems like we should be using triplediscrete sync

    Thanks for any help you can provide…

    Craig

  • Craig,

    yes, triplediscrete should be the right format for you based on the datasheet. You can also probe the signa after all these settings to make sure the signal are right.

    Regards,

    yihe