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connecting two 16 bit lpddr memories to one SDRC CS (as a 32bit memory) of OMAP3530

Jose42383
Prodigy 250 points
Other Parts Discussed in Thread: OMAP3530

hi,

I would like to know if it is possible to connect two 16bit LPDDR memories to a single CS of OMAP3530.

each memory module is 2gb, and together i would like them to appear as a single 4gb memory, with a 32bit interface.

can i connect d0-15 of each memory to d015, d16-31 of the OMAP, connect the address line to both of them, and work like that?

should i configure the CAS/RAS width as if it was a single 2gbX16 module?

 

Thanks,

Jose

  • 0
    TI__Expert 6735 points

    Jose:

    Are you using the CUS package for discrete memory?

    You can put the two LPDDRs both on CS0.  Must have one die in each SDRAM package, since limit of 2 loads on SDRC bus.

    SDRAM is configured in x-loader, in ./board/omap3evm/Omap3evm.c, in fcn config_3430sdram_ddr().

    This supports Micron and Hynix memory.  For OMAP3530 it has timing for 166MHz clock.

    May need to modify this code to support your 512MB (4Gb x 32) memory.  Not sure about RAS/CAS timing.

    Regards,

    Michael T

    PS: Please mark this post as answered via the Verify Answer button below if you think it answers your question.  Thanks!

     

     

  • 0 in reply to Michael T
    Prodigy 250 points

    hi,

    thank you for you answer.

    yes, i am using the CUS package and the memory is 2X micron 2gbit MT46H128M16LF. could you confirm it would work?

     

    I understand that if i use memories with 2 dies each, it won't work?

    assuming that i use memories with a single die, should i configure CS0 of the SDRC to be 32bit, 512MB, but use the RASWIDTH and CASWIDTH of a single memory?

     

    Thanks!

     

  • 0 in reply to Jose42383
    Prodigy 230 points

    Hi Jose

    Did you successed with this solution? I'm trying to use the same solution on our project.

  • 0 in reply to cai chengzuo
    Prodigy 230 points

    Hi TI guys

    Will you please let me know whether it is possible to design a 512MB memory system as mentioned above? As currently we are investigating this issue, and wish to get the answer ASAP. Thanks for your help in advance!

    Best Regards

  • 0 in reply to Michael T
    TI__Expert 6735 points

    Below is a quote from the OMAP3530 TRM, which confirms that CS0 can support 512MB.

    SDRC space

    Two SDRC chip-selects (sdrc_ncs0 and sdrc_ncs1) are available on the third quarter (Q2) of the

    addressing space to access SDRAM memories. The chip-selects have a programmable size (64, 128,

    256 or 512MB) in a total memory space of 1GB.

    The base address of the chip-select 0 (sdrc_ncs0) memory space is always 0x8000 0000. The base

    address of the chip-select 1 (sdrc_ncs1) memory space is programmable. The default value after reset

    is 0xA000 0000.

     

    Regards,

    Michael T