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AM5728: Cache usage on the ARM-A15 side

Nancy Wang
Expert 8210 points

Part Number: AM5728

Hi,

Is it possible to define the cache size under the bare metal of the A15 side, I did not find the API in the PDK, like CACHE_setL2Size under C6000?

  • 0
    TI__Mastermind 42135 points

    Hi Nancy,

    I don't think that it is possible. 

    Can you please tell what is your use case here? 

    Regards,
    Parth

  • 0 in reply to Parth Nagpal
    TI__Expert 8210 points

    Hi,

    Parth Nagpal said:
    Can you please tell what is your use case here?

    Customer defines the Ethernet sending and receiving data structure and array. When the data is defined in OCM1--3, the data can be sent and received normally. When these data are defined in the DDR space, the data cannot be sent and received normally. Guess it may be related to cache.

    After comment the CSL_A15_INIT_startup in pdk_am57xx_1_0_18\packages\ti\csl\arch\a15\src\csl_a15_startup.c, which is equivalent to not opening the cache and MMU, and then assigning the data to the DDR , and the Ethernet can work normally.

  • 0 in reply to Nancy Wang
    TI__Mastermind 42135 points

    Hi Nancy, 

    Nancy Wang said:
    When these data are defined in the DDR space, the data cannot be sent and received normally. Guess it may be related to cache.

    What do you mean by data cannot be sent and received normally? What are the error you are facing with assigning data to DDR space?

    Regards,
    Parth

  • 0 in reply to Parth Nagpal
    Prodigy 10 points

    Hi Parth

    data cannot be sent and received normally ,that means is that:when sending and receiving data structure and array defines in DDR,data write to sending data array,actually data cannot tramsmit out from sending array.also when other device through ethernet send data to my device,there is actually no data in the receive data array. However when  sending and receiving data structure and array defines in OCM1--3 area sent and receive all normally.DDR and OCM differ in DDR enable cache already.if disable DDR cache function and  sending and receiving data structure and array defines in DDR again,receive and send all normally