something is worng about LCD display

a snapshot will help to understand the problem better. 

If you can dump OSD/VENC registers, diagnosis will be easier.

when kernel boot ok:

after ./ application:

the valid display area is the little piece in the center

parameter of lcd :

no_of_outputs = LOGICPD_ENCODER_MAX_NO_OUTPUTS,
 .output[0] = {
        .output_name = VID_ENC_OUTPUT_LCD,
        .no_of_standard = LOGICPD_ENCODER_GRAPHICS_NUM_STD,
        .standards[0] = {
           .name = VID_ENC_STD_480x240,//VID_ENC_STD_640x480,
           .std = 1,
           .if_type = VID_ENC_IF_YCC8,
           .interlaced = 0,
           .xres = 480,//640,
           .yres = 240,
           .fps ={60, 1},// {30, 1},
           .left_margin = 80,//85
           .right_margin = 10, //70
           .upper_margin = 10,//32
           .lower_margin = 40,//11
           .hsync_len = 2,//9
           .vsync_len = 2,//9
           .flags = 0}, /* hsync -ve, vsync -ve */

register:

static void davinci_enc_set_ycc8(struct vid_enc_mode_info *mode_info)
{

 enableDigitalOutput(1);

 dispc_reg_out(VENC_VIDCTL, 0x141);
 /* set VPSS clock */
 davinci_writel(0x18, SYS_VPSS_CLKCTL);

 dispc_reg_out(VENC_DCLKCTL, 0);
 dispc_reg_out(VENC_DCLKPTN0, 0);

 /* Set the OSD Divisor to 1. */
 dispc_reg_out(VENC_OSDCLK0, 0x0);
 dispc_reg_out(VENC_OSDCLK1, 0x1);
 //dispc_reg_out(VENC_YCCCTL, 0x3);
 /* Clear composite mode register */
 dispc_reg_out(VENC_CVBS, 0);

 /* Set PINMUX1 to enable all outputs needed to support YYC8 */
 if (cpu_is_davinci_dm355()) {
  /* Enable the venc and dlcd clocks. */
  dispc_reg_out(VENC_CLKCTL, 0x11);
  davinci_cfg_reg(DM355_VOUT_FIELD_G70, PINMUX_RESV);
  davinci_cfg_reg(DM355_VOUT_COUTL_EN, PINMUX_RESV);
  davinci_cfg_reg(DM355_VOUT_COUTH_EN, PINMUX_RESV);
 } else if (cpu_is_davinci_dm365()) {
  /* DM365 pinmux */
  dispc_reg_out(VENC_CLKCTL, 0x11);
  davinci_cfg_reg(DM365_VOUT_FIELD_G81, PINMUX_RESV);
  davinci_cfg_reg(DM365_VOUT_COUTL_EN, PINMUX_RESV);
  davinci_cfg_reg(DM365_VOUT_COUTH_EN, PINMUX_RESV);
  //////////////////////////////modified,colorbar
 // u32 val=dispc_reg_in(VENC_VDPRO);
 // dispc_reg_out(VENC_VDPRO,val|(3<<8));
  //////////////////////////////////////
 } else {
  dispc_reg_out(VENC_CMPNT, 0x100);
  if (cpu_is_davinci_dm644x()) {
   davinci_cfg_reg(DM644X_GPIO46_47, PINMUX_RESV);
   davinci_cfg_reg(DM644X_GPIO0, PINMUX_RESV);
   davinci_cfg_reg(DM644X_RGB666, PINMUX_RESV);
   davinci_cfg_reg(DM644X_LOEEN, PINMUX_RESV);
   davinci_cfg_reg(DM644X_GPIO3, PINMUX_RESV);
  } else {
   davinci_cfg_reg(DM357_GPIO46_47, PINMUX_RESV);
   davinci_cfg_reg(DM357_GPIO0, PINMUX_RESV);
   davinci_cfg_reg(DM357_RGB666, PINMUX_RESV);
   davinci_cfg_reg(DM357_LOEEN, PINMUX_RESV);
   davinci_cfg_reg(DM357_GPIO3, PINMUX_RESV);
  }
 }

 if (cpu_is_davinci_dm355()) {
  davinci_writel(mode_info->left_margin,
          (DM355_OSD_REG_BASE + OSD_BASEPX));
  davinci_writel(mode_info->upper_margin,
          (DM355_OSD_REG_BASE + OSD_BASEPY));
 } else if (cpu_is_davinci_dm365()) {
  davinci_writel(mode_info->left_margin,
          (DM365_OSD_REG_BASE + OSD_BASEPX));
  davinci_writel(mode_info->upper_margin,
          (DM365_OSD_REG_BASE + OSD_BASEPY));
 } else {
  davinci_writel(mode_info->left_margin,
          (DM644X_OSD_REG_BASE + OSD_BASEPX));
  davinci_writel(mode_info->upper_margin,
          (DM644X_OSD_REG_BASE + OSD_BASEPY));
 }

 /* Set VIDCTL to select VCLKE = 1,
    VCLKZ =0, SYDIR = 0 (set o/p), DOMD = 0 */
 dispc_reg_merge(VENC_VIDCTL, 1 << VENC_VIDCTL_VCLKE_SHIFT,
   VENC_VIDCTL_VCLKE);
 dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_VCLKZ_SHIFT,
   VENC_VIDCTL_VCLKZ);
 dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_SYDIR_SHIFT,
   VENC_VIDCTL_SYDIR);
 dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_YCDIR_SHIFT,
   VENC_VIDCTL_YCDIR);

 dispc_reg_merge(VENC_DCLKCTL,
   1 << VENC_DCLKCTL_DCKEC_SHIFT, VENC_DCLKCTL_DCKEC);

 dispc_reg_out(VENC_DCLKPTN0, 0x1);

 davinci_enc_set_display_timing(mode_info);
 dispc_reg_out(VENC_SYNCCTL,
        (VENC_SYNCCTL_SYEV |
         VENC_SYNCCTL_SYEH | VENC_SYNCCTL_HPL
         | VENC_SYNCCTL_VPL));

 /* Configure VMOD. No change in VENC bit */
 dispc_reg_out(VENC_VMOD, 0x1011);
 dispc_reg_out(VENC_LCDOUT, 0x11);

}

pl refer to this link which describes VENC/OSD settings for dm365 LCD enabling.

http://processors.wiki.ti.com/index.php/How_to_program_VPBE_YCC8_digital_out

Is this standard?

This is page is published to help engineers to enable LCD. These are settings for 720x489 resolution LCD. You can correlate register setting with your case with the ones mentioned in the above link. That way you can figure out the problem.

Is this set by CCS or in the source code directly?Mine is 480x240,whether I only set the HINTVL and HVALID according the link?

OK,I will do that and tell you what happen.Thanks for your help