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TDA4VM: PLL LOCK status check - integration testing

Mert Aydın
Prodigy 30 points
Part Number: TDA4VM

Hi TI,

We have safety diagnostics activated for PLL slip detection. I wanted to verify this diagnostic with a integration testing. I am doing this with following approach:

  1. clear PLLX Frequency Control 0 Register to to 0x0000000  ( field name FB_DIV_INT )
  2. read lock status register ad evaluate
  3. write back original value

I am able to get desired result for only MAIN PLL. For other PLLs, the host hangs or crashes with following log:

ERROR:   Unhandled External Abort received on 0x80000001 at EL3!
ERROR:    exception reason=1 syndrome=0x92000210
PANIC in EL3.

Is there any suggestion to make it work after FB_DIV_INT  is altered ? or Would you suggest another approach to do integration testing?

Br,

Mert

  • 0
    TI__Mastermind 20200 points

    Hi Mert,

    I am somewhat concerned about this procedure as the clocks are used and therefore a bad frequency can cause errant behavior.

    The REF_DIV bitfield in FB_DIV_INT is not expected to see 0, so I am not sure how it reacts to this. 

    Your biggest concern is going to be (MCU_)PLL0 and the clock used for the processor you are using.  

    One alternative idea -- that may not meet your needs -- is that the DCC can be set to monitor the frequency ratio between two clocks. That is, you can show that the PLL output maintains a proper ratio to another clock; this approach does not look at the LOCK bit but does monitor the frequency (which is probably the key thing your safety metric requires).

    Kevin

  • 0 in reply to Kevin Lavery
    Prodigy 30 points

    Hi Kevin, thanks for the reply,

    Would you suggest anything to get error in PLL LOCK status registers?

  • 0 in reply to Mert Aydın
    TI__Mastermind 20200 points

    Mert,

    I can offer a suggestion that works in the MAIN PLL domains, and maybe a variant of the idea can work in the MCU domains. The key step is to bypass the PLL clock (so, for instance set bit 31 of PLLx_CTRL register). This step means that when the PLL loses lock, the clock does not corrupt the circuitry... For PLL8, I changed the clock source from OSC 0 to OSC 1 -- CLKSEL_PLL8.  I can see the lock status bit goes to 0; I then

    disable the PLL

    change the clock source back to OSC 0,

    re-enable the PLL

    after it is locked, I change the BYPASS to allow the PLL to propagate.

    Kevin