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C6678 SRIO 4x configuration

one and zero
Mastermind 18146 points

Hi Champs,

I'm trying to figure out how to configure SRIO to 4x mode.

In the User's Guide (sprugw1) I found on page 116:

"To change from one lane to 4 lanes there are 2 registers that need to be programmed: SP_IP_MODE Bits 31-30 need to be set to 0x1 and ..."

The SP_IP_Mode register doesn't exist anymore ....

Can I force a 4x configuration at all or is the lane configuration discovered automatically?

Please correct to information in the User's Guide. Thanks ...

 

Kind regards,

one and zero

  • 0
    TI__Intellectual 995 points

    One and Zero,

    You can configure the path mode via the RIO_PLM_SP_PATH_CTL register.  You'll want to modify the SRIO_RIO_PLM_SP_PATH_CTL_PATH_MODE field.

    Following is a code snippet based on the sample device_srio.c provided in the SRIO LLD.  The snippet shows how to configure the pad mode via the CSL APIs:

     

    /**

     *  Set pathMode variable equal to one of the following values:

     *    0 = lanes form four 1x ports                         (lanes form ports: 0, 1, 2 and 3)

     *    1 = lanes form one 2x port and two 1x ports  (lanes form ports: 0, 2 and 3)

     *    2 = lanes form two 1x ports and one 2x port (lanes form ports: 0, 1, and 2)

     *    3 = lanes form two 2x ports                         (lanes form ports: 0 and 2)

     *    4 = lanes form one 4x port                          (lanes form port: 0)

     */

     

      (hSrio is the handle obtained after opening the SRIO driver)

     

      Uint8    port, pathMode, bootCompleteFlag;

     

      /* Set mode for lanes to form one 4x port */

      pathMode = 4;

     

      /* Get boot-complete flag state */

      CSL_SRIO_GetBootComplete(hSrio, &bootCompleteFlag);

     

      /* Set boot-complete flag to 0 to enable writing to the SRIO registers if it was previously set to disable writing */

      If (bootCompleteFlag == 1)

        CSL_SRIO_SetBootComplete(hSrio, 0);

     

      /* Configure the path mode for all SRIO ports */

      For(port = 0; port < 4; port++)

          CSL_SRIO_SetPLMPortPathControlMode(hSrio, port, pathMode);

     

      /* Set boot-complete flag to 1 to disable writing to the SRIO registers if it was previously set to disable writing */

      If (bootCompleteFlag == 1)

          CSL_SRIO_SetBootComplete(hSrio, 1);

     

    Justin

  • 0
    TI__Mastermind 42545 points

    The width is set using the PLM Port Path Control Register.  See section 3.15.10 of the KeyStone Architecture Serial RapidIO (SRIO) SPRUGW1.  These registers should allow you to configure for x4.

    3.15.10 PLM Port(n) Path Control Register (PLM_SP(n)_PATH_CTL)

  • 0 in reply to Bill Taboada
    TI__Mastermind 18146 points

    Hi champs,

    thanks for your answers that makes it clear.

    Could we please update our documentation accordingly. The modes really should be explained int Section 3.15.10, but they are not.

    Also please remove the wrong references to SP_IP_MODE found on page 116.

    Kind regards,

    one and zero

  • 0 in reply to one and zero
    TI__Mastermind 42545 points

    We will submit you notes to the documentation team and get the document changed for the next release.  Thanks for pointing out the changes needed.