Hi experts,
Please let me confirm "Table 6-34. CK and ADDR_CTRL Routing Specification" on p.129 of the TMS320C6748 datasheet.(SPRS590G).
Q1: Do NO.5, 6 and 7 apply when DDR2/mDDR Dual-Memory is used? Or do they also apply when Single-Memory DDR2 is used?
Q2:For NO.6 and 7, each signal is connected to two DDR2/mDDR. Is it correct that each Routing length must be within 100 mils?
Q3:For NO.5, is it correct that the target signal must be kept within ±50 mils of the longest distance among the signal lines for DDR?
Best regards,
O.H