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TMS320C6748: About "CK and ADDR_CTRL Routing Specification”

Part Number: TMS320C6748

Hi experts,

Please let me confirm "Table 6-34. CK and ADDR_CTRL Routing Specification" on p.129 of the TMS320C6748 datasheet.(SPRS590G).

Q1: Do NO.5, 6 and 7 apply when DDR2/mDDR Dual-Memory is used? Or do they also apply when Single-Memory DDR2 is used?

Q2:For NO.6 and 7, each signal is connected to two DDR2/mDDR. Is it correct that each Routing length must be within 100 mils?

Q3:For NO.5, is it correct that the target signal must be kept within ±50 mils of the longest distance among the signal lines for DDR?

Best regards,
O.H

  • Hello Q.H, 

    Thank you for the query.

    Let me review the queries and update you.

    Regards,

    Sreenivasa

  • Hello Q.H, 

    Please refer below 

    Q1: Do NO.5, 6 and 7 apply when DDR2/mDDR Dual-Memory is used? Or do they also apply when Single-Memory DDR2 is used?

    In this specific example, this is for T topology routing.

    Q2:For NO.6 and 7, each signal is connected to two DDR2/mDDR. Is it correct that each Routing length must be within 100 mils?

    Since this is a T topology, this is correct.

    Q3:For NO.5, is it correct that the target signal must be kept within ±50 mils of the longest distance among the signal lines for DDR?

    As i  understand this is for the CK (DDR_CLK) and ADDR_CTRL net classes nominal trace length

    Regards,

    Sreenivasa

  • Hello Sreenivasa,

    Thank you for the reply.

    Q1: Do NO.5, 6 and 7 apply when DDR2/mDDR Dual-Memory is used? Or do they also apply when Single-Memory DDR2 is used?

    In this specific example, this is for T topology routing.

    From the answers, I understood that NO.5 is applicable regardless of the number of DDR2s, and NO.6 and 7 are applicable when two DDR2s are used, is that correct?

    Q2:For NO.6 and 7, each signal is connected to two DDR2/mDDR. Is it correct that each Routing length must be within 100 mils?

    Since this is a T topology, this is correct.

    I understood.

    Q3:For NO.5, is it correct that the target signal must be kept within ±50 mils of the longest distance among the signal lines for DDR?

    As i  understand this is for the CK (DDR_CLK) and ADDR_CTRL net classes nominal trace length

    As for NO.5, I understand that the trace length of DDR_CLKP / DDR_CLKN and DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE must be within ±50 mils of CACLM. Please let me confirm a definition of CACLM.

    In the note (4), it is stated that "CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes". This means that the trace length of the net class must be "within ±50 mils of the longest distance", and since CACLM is the longest distance, the shortest trace length in the net class should be within CACLM-50 mils, is this correct?

    Best regards,
    O.H

  • Hello Q.H

    Thank you for the inputs.

    Your understanding of CALCM matches the datasheet.

    Regarding Q1, your statement looks correct.

    Regards,

    Sreenivasa

  • Hello Sreenivasa,

    Thank you for the reply. I understood!

    Best regards,
    O.H

  • Hello O.H

    Good to hear and thank you.

    Regards,

    Sreenivasa