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TDA4VM: SciServer process task fail

Part Number: TDA4VM


HiTi Expert.

I found that,duirng startup, sci client request sci server so many times."Burst Request".and duirng load A72 and startup, always fail occur(see following picture).

Can you give me some detailed description that,if different clients request sci server at the same time, what shall happen?

  • Hi,

    I found that,duirng startup, sci client request sci server so many times."Burst Request".and duirng load A72 and startup, always fail occur(see following picture).

    From the logs, it looks like due to some reason sci server is not able to cater to the requests. Most probably this is happening because R5F is crashing. Can you please tell what application are you running on R5?

    Regards,
    Parth

  • Hi Parth

    R5 not crash,but Running well.

    This happens on my local project(base on SDK8.1) which transitions to AUTOSAR OS

  • Hello,

    Which OS is running on the A72? Is this based on another OS such as Linux provided in the TI Linux SDK?

    Regards,

    Erick

  • Hi Erick

    Linux is running on A72.

    Best Regards.

    TSL.

  • TS,

    One last clarification, which cores are you running the AUTOSAR OS on? Is this Classic AUTOSAR or Adaptive?

    Regards,

    Erick

  • Hi Erick

    AUTOSAR OS running on mcu1_0, as sci server

    you know,sci server only have 4 interrupts and 2 tasks.

    but sci client can be A72,mcu2_0,mcu3_0,c6x,c7x, DMSC(M3).which share the 4 interrupts

    so if all client cores(x > 4 INT,x is the client number) request sci server at the same time....then....

    i want to know some details about this case.....

    Best Regards.

    TSL.

  • Hi TSL,

    Can you share the complete logs? Also are the timeouts consistently come at that timeframe or it is different at different boots?
    DM firmware running on MCU1_0 is responsible for Resource & Power management. So by default all the other cores do
    request MCU1_0 for all the clocks. What is so different in your project?

    - Keerthy

  • Hi Keerthy,

    Also are the timeouts consistently come at that timeframe or it is different at different boots?

    ==>it is different at different boots.

     What is so different in your project?

    ==>DM firmware running on MCU1_0 is responsible for Resource & Power management,the same as default.

    Regards.

    TSL.

  • Hi TSL,

    I requested for the complete boot logs. Please provide them as an attachment for my reference.

    dev_id = 91 is failing. This is for eMMC. What is your boot media & where does your file system reside?

    - Keerthy

  • Hi Keerthy

    • I shall put the logs later,I need reproduce it again because i did not save the completed log.-->this is not my key question.

    • My key question is the 2nd picture:

    when all core request at the same time, for mcu1_0,is it possible to process all the requests?

    because in mcu1_0,only 4 interrupts but have to rx more than 4 cores' request at the same time.this is my key question.

    Further more,

    After I enable mcu1_0 cache fucntion,

    the phenomena sometimes occur,sometiems not occur in A72 side(from log view)

    --> I guess that,after enable cache function,mcu1_0 performance high,can process burst request.but still can not process all the burst which occur at the same time.

    but in mcu1_0 side,

    "Sciserver_processtask" still return -1,but the rating reduced after i enable mcu1_0 cache function.

    if cache function disabled, more than 10 times, -1 returned.

    after cache function enable, 2~5 times,-1 returned.

    --> I guess that,after enable cache function,mcu1_0 performance high,can process burst request.but still can not process all.

    So,the 2nd picture is my key question.

    Regards

    TSL.

  • So,the 2nd picture is my key question.

    I checked with our DM expert. secure proxy + ring accelerator provide HW FIFO which supports multiple-producer, single-consumer model.
    so multiple sciclient requests can be serviced on a single interrupt to DM. there are furthermore high and low priority interrupt request queues (RTOS all use high, Linux uses low). There are different queues for MCU and MAIN secure proxy this is what gets the 4x interrupts.

    The total number of messages which can be burst on these queues:

    software-dl.ti.com/.../sec_proxy.html and software-dl.ti.com/.../sec_proxy.html (see DM's nonsec_<high/low>_priority_rx queues)

    I hope your question is answered?

    - Keerthy

  • Hi Keerthy

    I will check and learn the answer.I still have some concerns.

    in interrupt process “Sciserver_tirtosUserMsgHwiFxn”,interrupt is disabled

    in task "Sciserver_tirtosUserMsgTask",interrupt is enable.see following picture.

    Question: why not all the process done in interrupt?but use task to do post process? the process done in task consume time? or some other reasons?

  • Hi,


    Question: why not all the process done in interrupt?but use task to do post process? the process done in task consume time? or some other reasons?

    We do not support nested interrupts so that is disabled & re-enabled after the task is done. Yes post processing is ideally done in task contest.

    - Keerthy