Hi all,
I'm in the process of writing a thesis for a M.S. in electrical engineering. Over the past few years I've developed a DSP processor in FPGA for space flight. The primary reason for doing this was there had been no other viable option. This is no longer true with TI's release of a space qualified C6701. In light of this, I would like to do a comparison against my custom processor and the C67XX. I've found a few benchmarks for performance here
TMS320C67X Assembly Benchmarks at Texas Instruments
This does not include two additional pieces of information that I'm looking for.
1) The number of gates used to implement the C67XX core
2) The number of cycles needed to "unscramble" the result of simultaneously computing two real FFTs with one single complex FFT computation. This would assume the buffer to be "unscrambled" has already been bit reversed.
3) Approximate release date of the space qualified C67XX class of processors.
The second one would be nice to have, but I really do need the first to do a proper comparison. So far I believe the C67XX architecture to be twice as fast as my implementation, but to use approximately 4-8 times the gates with all the execution units (no proof yet).
Thanks,
Brian Mokrzycki
