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Original question:

TDA4VM: TDA4 linux kernel camera problem

TDA4VM: Linux kernel problem with quad cameras

Justin Lu
Prodigy 50 points
Part Number: TDA4VM

Hi,

We got the MIPI CSI issue on Linux system.

We connected mono camera (1280x720@30) on the tp2855 decoder that is a quad camera video decoder and it is stuck when streaming on.

And we checked the interrupt table that increase 2 interrupts on dma-controller chan1 when using yavta to capture video from camera.

We measured the 2 pulse on MIPI clock and tp2855 send the MIPI data(D0-D3) always.

MIPI clock only got 2 pulse and the nothing else.

MIPI data

Which link frequency is correct when registering v4l2 control, V4L2_CID_LINK_FREQ?

We trace the cadence csi2rx and mipi-dphy driver and know the hs_clk_rate is equal link frequency.

And research the following information from the Technical Reference Manual .

Is it meant to be maximum link frequency that is 312.5MHz?

Is CSI_RX_BYTE_CLK equal to MIPI clock?

We calculated the 720p@30 MIPI clock is

1650(V total) * 750(H total) * 30fps * 16bit(YUYV) / 4 lane / 2 = 74.25MHz

But the tp2855 clock lane frequency support is the following table.

We tried to set up link frequency is 297M or 594M and the streaming still stuck.

How do we figure out the problem?

Our product should be supported quad cameras on Linux system, but we know Linux platform will be supported multiple cameras on September from TI FAE and the following E2E thread . We currently use the version is 08.01.00.07.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1065772/tda4vm-tda4-linux-kernel-camera-problem

Could you provide the multiple cameras patch to figure out the problem ASAP?

  • 0
    Prodigy 10 points

    Hi,

    The TP2855 is a HD/SD video decoder supporting HD-TVI video, NTSC/PAL CVBS video and common HD analog video format decoding from Techpoint. It supports up to 4 channel inputs, and a MIPI-CSI2 ouput.

    We had ported the TP2855 driver to TDA4 PSDK Linux and had the following problems about MIPI-CSI2.

    • Does the PSDK Linux 08.01.00.07 support the 4 channel virtual channels output from the V4l2 video device files? If not, which released version will support it, or could you provide the patch to us as soon as possible? Our product must be released in the end of this year, and the development of the applications is depended on the 4 channel video inputs.
    • We had try to use one channel video input and test our TP2855 driver and encountered the above problem. We would like the clarify some questions about the TDA4's CSI RX.
      1. Does the CSI_RX_BYTE_CLK mean the clock rate (in Hz) of the clock lane?
      2. Is the maximum MIPI clock rate 312.5MHz?
      3. What to look out when integrating our TP2855 driver with CSI RX driver? Is it enough to provide the link frequency via V4L2_CID_LINK_FREQ?
      4. Is it possible for CSIRX to affect the clock transfer of the CSI TX?

    Thanks

  • 0 in reply to Gavin Cho
    Prodigy 50 points

    Hi,

    TP2855 registered MIPI CSI clock rate is 297MHz per lane, and 4 Channels 4 Lanes for output.

    TDA4VM registered the LINK FREQ via v4l2 is 297000000.

    But TDA4VM cannot captured the data from MIPI CSI via v4l2.

    Already the TP2855 measured the CSI data(D0-D3) and CSI clock on the below.

    TP2855 side Clock N

    TP2855 side D0 N

    TDA4 side Clock N

    TDA4 side D0 N

    Any solution can verify TDA4VM MIPI CSI status (register or something else).

  • 0 in reply to Justin Lu
    TI__Guru** 113810 points

    Related to this issue, there was another E2E thread here, it has a few more details that can be useful for further debug:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1100442/sk-tda4vm-how-to-implement-quad-camera-driver-on-csi-interface 

  • 0 in reply to Gavin Cho
    TI__Guru* 80506 points

    Hi,

    Gavin Cho said:
    Does the PSDK Linux 08.01.00.07 support the 4 channel virtual channels output from the V4l2 video device files? If not, which released version will support it, or could you provide the patch to us as soon as possible? Our product must be released in the end of this year, and the development of the applications is depended on the 4 channel video inputs.

    Please find the branch here which supports Multi cam scenario for CSI in Linux https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/log/?h=ti-linux-5.10.y
    You could clone and use this kernel.
    Could you please check with this branch?

    Gavin Cho said:
    • Does the CSI_RX_BYTE_CLK mean the clock rate (in Hz) of the clock lane?
    • Is the maximum MIPI clock rate 312.5MHz?
    • What to look out when integrating our TP2855 driver with CSI RX driver? Is it enough to provide the link frequency via V4L2_CID_LINK_FREQ?
    • Is it possible for CSIRX to affect the clock transfer of the CSI TX?

    1. This is byte clock that is generated from the clock input

    2. Yes, max supported frequency is 2.5Ghz, so 2.5G/8 is 312.5MHz.

    3. Yes, V4L2_CID_LINK_FREQ is needed. It should also have the basic v4l2 subdev calls like s_stream so the stream can be enabled.

    4. No, both are independent.


    Regards,
    Nikhil

  • 0 in reply to Nikhil Dasan
    Prodigy 50 points

    Hi, Nikhil,

    We checked the register CSI_RX_IF_VBUS2APB_STREAM0_STATUS and CSI_RX_IF_VBUS2APB_ERROR_IRQS on Linux kernel 08.01.00.07 (commit 278e94c91409146ecc7396495051d020bf06d7cb)

    But we got the some error information on the below when using yavta to capture the video from TP2855(/dev/video2).

    1. Why is the stream enable but waiting for control data?

    2. Why is the register get the invalid access to the configuration? What the configuration?

    3. Does it figure out the mono camera issue(4 channels 4lanes) if we upgrade the kernel to the latest commit?

    Regard,

    Justin

  • 0 in reply to Justin Lu
    Prodigy 50 points

    Hi ,

    When the stream is enabled, it is stuck all the time.

    We verified the following registers and got some information.

    1. Read at address  0x04504104 (0xffff92fdd104): 0x80000111 (CSI_RX_IF_VBUS2APB_STREAM0_STATUS)

    The stream is enabled(RUNNING state) and READY state(Indicates the state of the pushback signal pixel_ready_if for this stream)

    Output to Stream FSM states: 1: STREAM_WAIT_CTRL_DATA // Expecting control data next

    Input to Stream FSM states: 1: PROT_WAIT_CTRL

    1. Read at address  0x04504028 (0xffff92b19028): 0x00001141 (CSI_RX_IF_VBUS2APB_ERROR_IRQS)

    A truncated header [short or Long] has been received

    Invalid access to the configuration register space.

    ECC error has been detected and corrected.

    Overflow detected in resynchronization FIFO between DPHY Lane Management and Protocol blocks.This will occur if sys_clk is not fast enough and should be increased since the byte clock frequency is fixed

    1. Read at address  0x04504008 (0xffffab814008): 0x43210400 (CSI_RX_IF_VBUS2APB_STATIC_CFG)

    Default is up to 4 virtual channels [3-bits] as per CSI2RX v1.3

    1. Read at address  0x04504060 (0xffff9971f060): 0x10000000 (CSI_RX_IF_VBUS2APB_INTEGRATION_DEBUG)

    csi2rx_fsm_state: WAIT_FOR_PACKET

    1. Read at address  0x04504020 (0xffffb9679020): 0x00000030 (CSI_RX_IF_VBUS2APB_INFO_IRQS)

    Either clock or any datalane has entered deskew

    Indicates non compliance with the MIPI specification although the core will continue to operate as normal.

    1. Read at address  0x0450410C (0xffffb8d4210c): 0x00000100 (CSI_RX_IF_VBUS2APB_STREAM0_CFG)

    FIFO_MODE: 01: Large Buffer [Fill Level Controlled].

    And we found the TP2855 issue when LS to HS mode.

    The invalid signal should be on the HS settle time because it cannot fix the issue on the hardware.

    Firstly, does it effect the TDA4VM to decode the MIPI CSI data?

    The TP2855 can adjust TLPX, THS-PREPARE and THS-ZERO from MIPI CSI Alliance.

    Second, How do we adjust the timing to meet TDA4VM expect?

    Lastly, What is HS-SETTLE default value(ns) on TDA4VM?

  • 0 in reply to Justin Lu
    TI__Expert 3430 points

    The question becomes: "Where to configure TDA4VM HS-Settle Time in CSI2-RX D-PHY?"

    The following is the HS-Settle Time register in Jacinto 6 but I can't find similar register in TDA4VM:

    Could you tell us where is the TDA4VM CSI-2 D-PHY register to setup THS_SETTLE timing parameter?
    What is the unit of value for THS_SETTLE?

    Thank you.