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TMDS64GPEVM: How to use shared memory for IPC between A53 <> R5F with linux

Alexander Baitinger
Prodigy 20 points

Part Number: TMDS64GPEVM

Hello support team,

 

i'm currently working with the AM64x GPEVM and i was already successful in running some examples like the "gpio led blink" or the "ipc rpmsg echo linux r5fss0-0 freertos" in combination with your linux userspace application "ti-rpmsg-char" to send messages between A53 and the R5Fss0-0.

Now, i want to send data, which is more than 512 bytes large and therefore i need to use the shared memory approach. Could you please provide some example on how to initialize some data in shared memory by the R5F core, like a large buffer (>512 bytes), which can then be shared via a pointer in a rpmsg to A53 in alinux userspace application?

I already searched through the forum and also your documentation but i was not able to find some good or matching example. The "ipc spinlock sharedmem" example goes into this direction but the volatile variable just gets incremented and it is only between the FREERTOS cores, if i'm correct.

 

Thanks in advance for your help!

 

BR

Alex

  • 0
    TI__Guru** 100660 points

    Hello Alex,

    Glad to hear that the original examples have been working for you!

    We do not currently have a shared memory example for AM64x. However, we are working on an example where a section of shared memory is exposed up to Linux userspace, and RPMsg is used to send notifications between Linux userspace and the R5F core when data in the shared memory is ready for consumption. This example will be published in one of the AM64x SDK releases in 2H2022.

    I believe that the MCU+ team is also working on a shared memory example between two MCU+ cores using IPC_Notify instead of IPC_RPMsg. If that is also interesting to you, I can do some digging to check on the development timeframe of that example.

    Do note that RPMsg is useful for many applications, but it might not be the right fit if the IPC between the Linux core and the MCU+ core is in a tight control loop. Reference this FAQ for more information around ensuring that computations occur within a set cycle time: e2e.ti.com/.../faq-sitara-multicore-system-design-how-to-ensure-computations-occur-within-a-set-cycle-time

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 20 points

    Hello Nick,

    thanks for your quick response and the informations.

    That's unfortunately that there is no example available yet. Could you please give me some more specific date for the example release, I can't really wait for an undefined time, because this implementation is quite essential to have for performance tests.

    If you have some other resources available for this topic i would appreciate it, if you could share them with me. 

    BR

    Alex

  • 0 in reply to Alexander Baitinger
    TI__Guru** 100660 points

    Hello Alex,

    Timeframe for TI example

    Let me sync with the developer to make sure I am telling you the correct 2H2022 SDK release.

    IPC resources

    By "this topic", are you thinking about any subjects in particular? I am actively working on several IPC documents, so depending on your needs I can point you to existing pages in the Linux SDK or MCU+ SDK, or we can discuss topics that are under development and will be added to the AM64x Linux Academy in the near future.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Guru** 100660 points

    Hello Alex,

    We are planning to add the shared memory IPC example in the AM64x Linux Processor SDK 8.4 release (in the August / September timeframe).

    Note that manhours have been allocated to work on this example, but the code is not actually written yet. So there is the potential that the example will not be ready for the SDK 8.4 release. If that happens, then the shared memory IPC example would be added in the AM64x Linux Processor SDK 8.5 release (in the October / November timeframe).

    Regards,

    Nick