How could I init ddr on A72?

Hi Nathan,

The U-Boot image size is > 1 MB. The internal SRAM of MCU can not accommodate that. Hence we have R5 SPL doing the DDR init.

All the configuration happens using the arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi.

Driver in the U-Boot repo: "drivers/ram/k3-ddrss/k3-ddrss.c"

Best Regards,
Keerthy

Hi Keerthy,

About the u-boot image size, we want run it on MSMC SRAM, so we can avoid this problem.

We want to init DDR on A72 because the inline ecc region need preload by dma, but this would affect AutoSAR boot time.

We have tryied this idea but We ran into problems with DDR stability.I suspect that the DDR is unstable due to the DDR clock configuration problem.

BR

Nathan

Hi Nathan,

What is the added latency with R5 SPL doing the inline ecc Initialization? My question is more towards understanding
what is your end goal to meet the inline ecc init timing & whether that can accomplished by switching inline ECC init to A72 side.

- Keerthy

Hi Keerthy,

Before I enable the ECC check, I need initialize the region to be protected with a known pattern.And this is a very time consuming operation even i use the bist engine to initialize which would be faster than DMA.

My goal is to complete DDR initialization and ecc initialization as soon as possible.So I want to do DDR initialization and ECC initialization on the A72, and if this goal cannot be achieved, I want to do ECC initialization on the A72.

BR

Nathan

Nathan,

The whole exercise is currently done on R5 SPL. The recommendation was to enable the Ecc for a limited small region. Irrespective of where you init the
the latency will surely be there either on R5 or A72. As of now A72 SPL memcpy is not so optimized. Hence I am requesting you to enable from R5 side.

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/08_02_00_03/exports/docs/devices/J7/linux/Release_Specific_Release_Notes.html

So you might still face the same delay from A72 side as well.

- Keerthy