Is writing/reading a ram cell with 32bits an atomic operation in OMAPL138 ?

Peng,

Although you are using BIOS, it appears your question is one of raw arbitration between the cores.  I'm going to go ahead and move this query to the OMAP-L1x forum in hopes you'll get a faster response there.

Dave

Thanks, David.

Anybody can give some suggestion?

Thanks!

Peng,

   You might be interested to check out DSP/LINK article on our wiki. It was developed in order to remove the headache away from the inter-processor communication between the ARM & DSP cores by creating an API.

Thanks, Drew,

we did use DSPLink to transfer data between two cores.

For performance concern, we want to use share memory to switch large data between ARM & DSP, but not sure whether we can write/read a same ram cell(4 bytes) from ARM & DSP simultaneously.

Any doc about this problem ?

Thanks.

Sorry, Drew, I think I didn't describe my question clearly.

I'm not mean the shared memory on OMAP chip.

Actually, we reserved a piece of DSP memory in SDRAM (from datasheet, should be DDR2 RAM), and on ARM, we mapped this memory into Linux virtual memory. There are some fileds would be changed by ARM&DSP in this shared memory. For a single field with 4 bytes size (aligned with 4 bytes too), what would happen if ARM & DSP change it at the same time? The change would be overwriten by the second writing ? or this field would hold a conflict value ?

It's OK for us if the change would be totally overwriten by the second writing; but if this field would hold a conflict data, it is real a problem for us.

Thanks.

Peng,

For a single 32 bit write to the same peripheral (DDR2 or EMIFx), there is arbitration logic which will typically allow one write at a time.

For example, the peripheral configuration (CFG) port  is 32 bit wide, a single write by both the ARM and DSP cores to the same peripheral address both  rely on an internal bus infrastructure to gain access to a shared memory mapped address. This internal bus infrastructure has built in arbitration logic to determine which CPU get's priority to access the register first. From this standpoint, a memory write to the same address by two masters is atomic.

The arbitration for access to the same memory is determined by the priority of the bus master. The priority of the master is configurable by the OMAP-L138 SYSCFG registers (Refer to the OMAP-L138 System Reference Guide for details). Additionally, this Wiki Article explains the bus arbitration of the Switched Central Resources (SCR) of the interconnect fabric. I think this will help answer part of your question.

In terms your situation of a 4 byte write to a memory space, the answer is a little more complex. In theory, if there are two pending accesses to the same address space from two masters, the master with higher priority will always win. If the masters share the same priority, each will get a turn to access the memory in a round-robin manner. (This is outlined in the wiki), however there can be cases in which one read/write can 'sneak in' from a lower priority bus master when you don't want it to. One example of when this can happen is  when the master with the higher priority is interrupted in the middle a sequence of 4 contiguous 4 byte writes. In this case, the bus infrastructure will (automatically) schedule and submit the next highest priority request(s). In this case, the memory will become corrupted.

If you are sharing a single memory space for both the ARM and the DSP to read/write to with more than a single 32 bit read/write access, it is expected that your implement some level of messaging between the two cores so they don't corrupt each other.

Hi, Drew, thanks for your great help.

So, can we say that:

1. if ARM & DSP read/write a same memory address that is a register, we can think the operation is atomic ?

2. if ARM & DSP read/write a same memory address that is DDR, the read/write operation may make the data corrupted ?

And one more question:

Drew Abuan said:

however there can be cases in which one read/write can 'sneak in' from a lower priority bus master when you don't want it to. One example of when this can happen is  when the master with the higher priority is interrupted in the middle a sequence of 4 contiguous 4 byte writes.

in what condition, the master would be interrupted when it  is reading/writing memory?

Thanks.

PENG HUANG said:

1. if ARM & DSP read/write a same memory address that is a register, we can think the operation is atomic ?

If the register is internal to the Part - yes - it should be atomic.

PENG HUANG said:

2. if ARM & DSP read/write a same memory address that is DDR, the read/write operation may make the data corrupted ?

Possibly - It depends on how you structure the code, arbitration levels, etc. It is up to the application to guarantee that there is no corruption when multiple masters are accessing the same resource

PENG HUANG said:

in what condition, the master would be interrupted when it  is reading/writing memory?

That was a generic example, however in general Interrupts are asynchronous in terms of CPU execution, so they could occur at any time.