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TDA4VM: ECC Aggregator and RAT

Part Number: TDA4VM

Hi ,

I want to access the ecc aggregator address from the r5f within the MAIN domain. The code is 

result = SDL_ECC_init(SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0, &ECC_Test_MAINMSMCA0ECCInitConfig);

I was initialize the OSAL with the osal_interface and using it's addrTranslate function SDL_TEST_addrTranslate.

#define PBIST_RAT_CFG_BASE CSL_MCU_ARMSS_RAT_CFG_BASE

static SDL_OSAL_Interface osal_interface =
{
    .enableInterrupt = (pSDL_OSAL_interruptFunction) SDL_enableInterrupt,
    .disableInterrupt = (pSDL_OSAL_interruptFunction) SDL_disableInterrupt,
    .registerInterrupt = (pSDL_OSAL_registerFunction) SDL_registerInterrupt,
    .deregisterInterrupt = (pSDL_OSAL_deregisterFunction) HwiP_delete,
    .globalDisableInterrupts = (pSDL_OSAL_globalDisableInterruptsFunction) SDL_globalDisableInterrupts,
    .globalRestoreInterrupts = (pSDL_OSAL_globalRestoreInterruptsFunction) SDL_globalRestoreInterrupts,
    .printFxn = (pSDL_OSAL_printFunction) printf,
    .delay = (pSDL_OSAL_delayFunction) Osal_delay,
    .addrTranslate = (pSDL_OSAL_addrTranslateFunction) SDL_TEST_addrTranslate
};

ret = SDL_OSAL_init(&osal_interface);

But when I run this application, it was hang in the CSL_ratDisableRegionTranslation function.

The overall calling relationship is as follows:

SDL_ECC_init
    SDL_ECC_mapEccAggrReg
        SDL_OSAL_addrTranslate
            gOSAL_Interface->addrTranslate
                SDL_TEST_addrTranslate
                    CSL_ratDisableRegionTranslation
                        CSL_ratGetMaxRegions
                            CSL_REG32_FEXT

I need help with the following points:
1) On the TDA4 chip, is it correct that I found the RAT register named CSL_MCU_ARMSS_RAT_CFG_BASE?
2) The above code I coded with reference to SDL, is there any problem? Why is it hang in the RAT address translation function?

  • Hi Zhang,

    Can you please share what SDL_OSAL_init is doing? This API does not seem to be from PDK.
    Also, please mention the SDK version you are using?

    Regards,
    Parth

  • Hi Parth,

    The SDL_OSAL_init function is provided by the SDL in the RTOS SDK8.2 Link: PROCESSOR-SDK-RTOS-J721E Software development kit (SDK) | TI.com.

    sdl/osal/src/sdl_osal.c
    
    int32_t SDL_OSAL_init(SDL_OSAL_Interface *osalInterface)
    {
        SDL_ErrType_t ret = SDL_PASS;
    
        if (osalInterface == NULL_PTR)
        {
            ret = SDL_EINVALID_PARAMS;
        }
        else
        {
            gOSAL_Interface = osalInterface;
        }
    
        return ret;
    }
    

  • Hi Parth,

    About this thread, could you give me some suggestions ? Thanks.

  • Can the base address "CSL_MCU_ARMSS_RAT_CFG_BASE 0x40f90000U" be accessed in the MAIN domain MCU core?

  • From the TRM 8.4.1, I fould the RAT module can be access from the mcu in MAIN domain. Where can I find it's base address.

    From the code path with pdk_jacinto_08_02_00_21/packages/ti/csl/test/core-r5/core_r5_rat_test.c , it seems that only defined the address access from the MCU domain.

    int32_t cslcore_r5_ratTest(void)
    {
        /* Declarations of variables */
        CSL_RatExceptionInfo  ratExceptionInfo;
        int32_t    testResult = CSL_APP_TEST_PASS;
    #if defined (SOC_AM65XX)
        CSL_ratRegs *pRatRegs = (CSL_ratRegs *)CSL_MCU_RAT_CFG_BASE;
    #elif defined (SOC_AM64X)
        CSL_ratRegs *pRatRegs = (CSL_ratRegs *) CSL_R5FSS0_RAT_CFG_BASE;
    #elif defined (SOC_J721E)
        CSL_ratRegs *pRatRegs = (CSL_ratRegs *) CSL_MCU_ARMSS_RAT_CFG_BASE;
    #elif defined (SOC_J7200)
        CSL_ratRegs *pRatRegs = (CSL_ratRegs *) CSL_MCU_R5FSS0_RAT_CFG_BASE;
    #else
        # error "RAT register BASE not defined"
    #endif
    

  • Hi,

    Looking at the TRM documentation, the RAT register base addresses are defined in the modules which use the RAT.

    Using the Main Domain R5s as an example the base address is shown below as 0x0FF90000, see (2) in below TRM snippet.

    An MCU2_0 (R5 main domain) coding example in SDK RTOS 8.2, can be seen using the 0x0FF90000 base address in the below file.

    packages/ti/csl/example/ospi/ddr_memory_benchmarking/main_rtos.c

    Regards,

    kb

  • Thanks KB.

    Best Regard.

  • Hi KB,

    Another question about ECC AGGR, I failed in get the ecc aggr ramnums. The line 9 return the pNumRams is 0. And I found the pEccAggrRegs->STAT was can be set, also equal to 0.

    int32_t SDL_ecc_aggrGetNumRams(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pNumRams)
    {
        int32_t    retVal = SDL_EBADARGS;
    
        if ( pEccAggrRegs != NULL_PTR )
        {
            if (pNumRams  != NULL_PTR)
            {
                *pNumRams = (uint32_t)SDL_REG32_FEXT(&pEccAggrRegs->STAT, ECC_AGGR_STAT_NUM_RAMS);
                 retVal   = SDL_PASS;
            }
        }
        /* Return the API success/fail with value in the address provided by caller */
        return (retVal);
    }

    Could you give some suggestions about this problem ?

  • Hi KB,

    I called the function "ECC_funcTest" defined in sdl/example filename ecc_trigger.c in the mcu core of MAIN domain. 

    But it report the number of rams is 0 as memtions as above.

    The full log is as following, could you please tell me where wrong with the code ?

    [MCU3_0]      3.963121 s: CIO: Init ... Done !!!
    [MCU3_0]      3.963197 s: ### CPU Frequency = 1000000000 Hz
    [MCU3_0]      3.963238 s: APP: Init ... !!!
    [MCU3_0]      3.963264 s: SCICLIENT: Init ... !!!
    [MCU3_0]      3.963538 s: SCICLIENT: DMSC FW version [22.1.1--v2022.01 (Terrific Llam]
    [MCU3_0]      3.963586 s: SCICLIENT: DMSC FW revision 0x16
    [MCU3_0]      3.963635 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU3_0]      3.963673 s: SCICLIENT: Init ... Done !!!
    [MCU3_0]      3.963702 s: MEM: Init ... !!!
    [MCU3_0]      3.963742 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ db000000 of size 8388608 bytes !!!
    [MCU3_0]      3.963816 s: MEM: Init ... Done !!!
    [MCU3_0]      3.963843 s: IPC: Init ... !!!
    [MCU3_0]      3.963907 s: IPC: 8 CPUs participating in IPC !!!
    [MCU3_0]      3.985068 s: IPC: Init ... Done !!!
    [MCU3_0]      3.985136 s: APP: Syncing with 7 CPUs ... !!!
    [MCU3_0]      4.709536 s: APP: Syncing with 7 CPUs ... Done !!!
    [MCU3_0]      4.709580 s: REMOTE_SERVICE: Init ... !!!
    [MCU3_0]      4.711653 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU3_0]      4.711738 s:  VX_ZONE_INIT:Enabled
    [MCU3_0]      4.711779 s:  VX_ZONE_ERROR:Enabled
    [MCU3_0]      4.711809 s:  VX_ZONE_WARNING:Enabled
    [MCU3_0]      4.712844 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target IPU2-0
    [MCU3_0]      4.712909 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [MCU3_0]      4.712948 s: APP: OpenVX Target kernel init ... !!!
    [MCU3_0]      4.712982 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU3_0]      4.713015 s: APP: Init ... Done !!!
    [MCU3_0]      4.714161 s:
    [MCU3_0]      4.714203 s:  ECC_Test_init: Init MCU ESM complete
    [MCU3_0]      4.761676 s: Ruifeng SDL_ECC_init 895 retVal = 0
    [MCU3_0]      4.761737 s: Ruifeng SDL_ECC_mapEccAggrReg 256
    [MCU3_0]      4.761788 s: Ruifeng SDL_ECC_mapRatEccAggrBaseAddress 221
    [MCU3_0]      4.761838 s: rat version = 1719677184
    [MCU3_0]      4.761883 s: Ruifeng CSL_ratConfigRegionTranslation 574
    [MCU3_0]      4.761932 s: Ruifeng CSL_ratConfigRegionTranslation 579
    [MCU3_0]      4.761988 s: Ruifeng CSL_ratValidateTranslationConfig 140 Input regionIndex = 1
    [MCU3_0]      4.762043 s: Ruifeng CSL_ratValidateTranslationConfig 143
    [MCU3_0]      4.762110 s: Ruifeng CSL_ratValidateTranslationConfig 158 (uint64_t)pTranslationCfg->baseAddress & (regionSize-1UL) = 0
    [MCU3_0]      4.762210 s: Ruifeng CSL_ratValidateTranslationConfig 160 translatedAddress = 0x4d20000000 regionSize = 0x400 (pTranslationCfg->translatedAddress     & (regionSize-1UL) = 0
    [MCU3_0]      4.762314 s: Ruifeng CSL_ratValidateTranslationConfig 162 CSL_ratIsRegionOverlap(pRatRegs, regionIndex, pTranslationCfg ) = 0
    [MCU3_0]      4.762384 s: Ruifeng CSL_ratConfigRegionTranslation 589
    [MCU3_0]      4.762432 s: Ruifeng CSL_ratConfigRegionTranslation 593
    [MCU3_0]      4.762478 s: Ruifeng CSL_ratConfigRegionTranslation 601
    [MCU3_0]      4.762536 s: Ruifeng CSL_ratValidateTranslationConfig 140 Input regionIndex = 1
    [MCU3_0]      4.762606 s: Ruifeng CSL_ratValidateTranslationConfig 158 (uint64_t)pTranslationCfg->baseAddress & (regionSize-1UL) = 0
    [MCU3_0]      4.762713 s: Ruifeng CSL_ratValidateTranslationConfig 160 translatedAddress = 0x4d20000000 regionSize = 0x400 (pTranslationCfg->translatedAddress     & (regionSize-1UL) = 0
    [MCU3_0]      4.762815 s: Ruifeng CSL_ratValidateTranslationConfig 162 CSL_ratIsRegionOverlap(pRatRegs, regionIndex, pTranslationCfg ) = 0
    [MCU3_0]      4.762893 s: Ruifeng CSL_ratConfigRegionTranslation 603 retVal = 1
    [MCU3_0]      4.762942 s: Ruifeng CSL_ratConfigRegionTranslation 609
    [MCU3_0]      4.762993 s: Ruifeng SDL_TEST_addrTranslate 266 result = 1
    [MCU3_0]      4.763042 s: Ruifeng SDL_ECC_mapRatEccAggrBaseAddress 223
    [MCU3_0]      4.763094 s: Ruifeng SDL_ECC_mapEccAggrReg 261 mapIdx = 0
    [MCU3_0]      4.763143 s: Ruifeng SDL_ECC_mapEccAggrReg 266
    [MCU3_0]      4.763188 s: Ruifeng SDL_ECC_mapEccAggrReg 271
    [MCU3_0]      4.763237 s: Ruifeng SDL_ECC_init 901 retVal = 0
    [MCU3_0]      4.763277 s: Ruifeng SDL_ECC_init 909
    [MCU3_0]      4.763319 s: Ruifeng SDL_ecc_aggrDisableAllIntrs 1536
    [MCU3_0]      4.763363 s: Ruifeng SDL_ecc_aggrDisableAllIntrs 1540
    [MCU3_0]      4.763410 s: Ruifeng SDL_ecc_aggrDisableIntrs 1489
    [MCU3_0]      4.763457 s: Ruifeng SDL_ecc_aggrToggleIntrsEnable 404
    [MCU3_0]      4.763504 s: Ruifeng SDL_ecc_aggrToggleIntrsEnable 410
    [MCU3_0]      4.763551 s: Ruifeng SDL_ecc_aggrGetNumRams 475
    [MCU3_0]      4.763594 s: Ruifeng SDL_ecc_aggrGetNumRams 478
    [MCU3_0]      4.763663 s: Ruifeng SDL_ecc_aggrGetNumRams 483 pEccAggrRegs->STAT = 0x0 *pNumRams = 0 retVal = 0
    [MCU3_0]      4.763722 s: Ruifeng SDL_ecc_aggrGetNumRams 487
    [MCU3_0]      4.763772 s: Ruifeng SDL_ecc_aggrToggleIntrsEnable 412 sdlRet = 0
    [MCU3_0]      4.763834 s: Ruifeng SDL_ecc_aggrToggleIntrsEnable 440 sdlRet = 0 retVal = 1
    [MCU3_0]      4.763891 s: Ruifeng SDL_ecc_aggrDisableIntrs 1494 operation = 1
    [MCU3_0]      4.763946 s: Ruifeng SDL_ecc_aggrDisableIntrs 1506 retVal = 0
    [MCU3_0]      4.763999 s: Ruifeng SDL_ecc_aggrDisableAllIntrs 1542 retVal = 0
    [MCU3_0]      4.764046 s: Ruifeng SDL_ecc_aggrDisableIntrs 1489
    [MCU3_0]      4.764091 s: Ruifeng SDL_ecc_aggrToggleIntrsEnable 404
    [MCU3_0]      4.764138 s: Ruifeng SDL_ecc_aggrToggleIntrsEnable 410
    [MCU3_0]      4.764182 s: Ruifeng SDL_ecc_aggrGetNumRams 475
    [MCU3_0]      4.764225 s: Ruifeng SDL_ecc_aggrGetNumRams 478
    [MCU3_0]      4.764287 s: Ruifeng SDL_ecc_aggrGetNumRams 483 pEccAggrRegs->STAT = 0x0 *pNumRams = 0 retVal = 0
    [MCU3_0]      4.764343 s: Ruifeng SDL_ecc_aggrGetNumRams 487
    [MCU3_0]      4.764391 s: Ruifeng SDL_ecc_aggrToggleIntrsEnable 412 sdlRet = 0
    [MCU3_0]      4.764451 s: Ruifeng SDL_ecc_aggrToggleIntrsEnable 440 sdlRet = 0 retVal = 1
    [MCU3_0]      4.764508 s: Ruifeng SDL_ecc_aggrDisableIntrs 1494 operation = 1
    [MCU3_0]      4.764559 s: Ruifeng SDL_ecc_aggrDisableIntrs 1506 retVal = 0
    [MCU3_0]      4.764619 s: Ruifeng SDL_ecc_aggrDisableAllIntrs 1548 retVal = 0
    [MCU3_0]      4.764669 s: Ruifeng SDL_ecc_aggrGetNumRams 475
    [MCU3_0]      4.764711 s: Ruifeng SDL_ecc_aggrGetNumRams 478
    [MCU3_0]      4.764774 s: Ruifeng SDL_ecc_aggrGetNumRams 483 pEccAggrRegs->STAT = 0x0 *pNumRams = 0 retVal = 0
    [MCU3_0]      4.764831 s: Ruifeng SDL_ecc_aggrGetNumRams 487
    [MCU3_0]      4.764889 s: Ruifeng SDL_ECC_init 916 sdlResult = 0 numMemRegions = 0
    [MCU3_0]      4.764943 s: Ruifeng SDL_ECC_init 919 sdlResult = 0
    [MCU3_0]      4.764991 s: Ruifeng SDL_ECC_init 922 retVal = -1
    [MCU3_0]      4.765041 s: Ruifeng SDL_ECC_init 944 retVal = -1
    [MCU3_0]      4.765088 s: Ruifeng SDL_ECC_init 954 retVal = -1
    [MCU3_0]      4.765137 s: Ruifeng SDL_ECC_init 1010 retVal = -1
    [MCU3_0]      4.869619 s: APP: Run ... !!!
    [MCU3_0]      4.869656 s: IPC: Starting echo test ...
    [MCU3_0]      4.873083 s: APP: Run ... Done !!!
    [MCU3_0]      4.874721 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.]
    [MCU3_0]      4.874855 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.]
    [MCU3_0]      4.874973 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[.]
    [MCU3_0]      4.875078 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.]
    [MCU3_0]      4.875185 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU3_0]      4.902715 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
    

  • Hi,

    TI tests the SDL release on MCU1_0 in the MCU Safety Island, and in general MCU1_0 is the expected location for SDL to run for a safety solution.

    For the code to function on MCU3_0, but there may be some porting that has to occur.   

    In regards to the issue described, is the rest of the system idle at this point, or are other cores in use?

    Thanks,

    kb

  • Hi KB,

    Thanks for your reply.

    We are still in the development stage of functional safety. When the above problem occurs, most of the CPUs in the system are idle.

    1) Is the ecc aggr ram number equal to 0 related to the CPU usage?
    2) We plan to implement part of the functional safety on the mcu3_0 of the main domain. Is this design feasible and reasonable?
    3) According to the printing of the log, the value in the read ecc aggr register is 0. Where can I see the device manual of each ecc aggr? How should I proceed with the next analysis?

  • Hi KB,

    The above question, please help to check, thanks.

  • Hi,

    I find this thread is starting to cover topics not necessarily capture by the title, and some of the topics seem to be overlapping with other e2e threads.

    (+) TDA4VM: How should the ECC AGGR type in TRM match the type and subtype in SDL? - Processors forum - Processors - TI E2E support forums

    Has the initial question of "ECC Aggregator and RAT" been addressed?  If so can this thread be closed, and a new thread be created to cover (1) (2) and (3) as needed?

    Thanks,

    kb