66AK2G12: QSPI boot configuration by ROM code

Koichiro Tashiro

Part Number: 66AK2G12

Hi,

My customer is using QSPI boot (96MHz) and device is boot-up correctly.
But there are a few unclear points.

Q1) According to TRM(spruhy8i.pdf) Table 4-24, delay values (byte offset 48 and 50) are 0x1010 for QSPI 96MHz.
The customer checked Boot Parameter Table at 0x0C0F4100 by CCS and found these values are 0xC0C0 and 0x2E2E.

QSPI_DEV_DELAY_REG is also configured as 0xC0C02E2E.

Is the TRM description wrong?

Q2) According to QSPI_DEV_DELAY_REG description, each bit field specifies a delay with QSPI_REF_CLK cycles (= 384MHz module clock).

So if QSPI_DEV_DELAY_REG=0xC0C02E2E, each parameter is calculated as below.
D_NSS_FLD = 192(dec) x 2.6ns = ~500ns
D_AFTER_FLD = 46(dec) x 2.6ns = ~120ns
D_INIT_FLD = 46(dec) x 2.6ns = ~120ns

But what customer observed in waveforms are much less. D_AFTER_FLD and D_INIT_FLD are ~10ns.

I think something wrong in TRM description.
What is correct calculation to get these delay periods?

Thanks and regards,
Koichiro Tashiro

over 4 years ago

0 JJD over 4 years ago

TI__Guru* 94451 points

I think the TRM is incorrect in the parameter tables.

With the 0x2E values, you should actually should be seeing CS assert 1/2 clock cycle + 46*2.6ns = 20.8ns + 120ns = 140.8ns, and similar delay for the deassertion after the last bit transfer. It appears that you are only seeing the default 1/2 clock cycle. so i'm not sure why. Are you programming the delay values when the controller is idle? This is a requirement for these registers.

Regards

James

0 Koichiro Tashiro over 4 years ago in reply to JJD

TI__Mastermind 22945 points

Hi James,

JJD said:
Are you programming the delay values when the controller is idle?

The customer does not touch QSPI_DEV_DELAY_REG at all. So these values are programmed by ROM code.

Thanks and regards,
Koichiro Tashiro

0 Koichiro Tashiro over 4 years ago in reply to Koichiro Tashiro

TI__Mastermind 22945 points

Hi James,

The customer found he observed wrong waveforms. Now he checked correct waveforms and confirmed these timings are aligned to QSPI_DEV_DELAY_REG=0xC0C02E2E.

So this item is considered as closed now.

Thanks and regards,
Koichiro Tashiro

0 PaulM over 4 years ago in reply to Koichiro Tashiro

TI__Mastermind 30265 points

Thank you for following up and letting us know the issue is resolved. I'll close the ticket.

--Paul

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66AK2G12: QSPI boot configuration by ROM code