AM6442: PCIe SERDES interface routing guidelines.

Koichiro Tashiro

Part Number: AM6442

Hi,

My customer is designing their PCB and referring below document.
https://www.ti.com/lit/ug/spruiy5a/spruiy5a.pdf

In section 5, there is below description;
"The transmit pair should be routed away from the SoC on the top layer leaving a gap without blocking vias."
Customer understood this means TX signals should be routed on other layer than the top layer where the SoC is.
But Figure 5-1 shows TX signals are routed on the top layer (the same layer where the SoC is).

Is the description wrong?

Currently TX, RX and CLK are all routed on the top layer in customer's PCB design.
They are planning to move RX and CLK signals to other layers as same as Figure 5-1.
Do you have any recommendation?

Thanks and regards,
Koichiro Tashiro

over 3 years ago

0 Kallikuppa Sreenivasa over 3 years ago

TI__Guru**** 192189 points

Hello Koichiro Tashiro,

Thank you for the query.

Let me review internally and update you.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 192189 points

Hello Koichiro Tashiro,

Thank you for following.

The transmit pair should be routed away from the SoC on the top layer leaving a gap without blocking vias

Thee is some confusion around the wording and this may not be fully valid.

Regarding the signal routing i would recommend following the layout. Please take care of routing the traces symmetrically with the AC coupling caps.

Please be sure to provide clearance for the differential tracks from the other traces.

Regards,

Sreenivasa

0 Koichiro Tashiro over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Mastermind 22945 points

Hi Sreenivasa,

Thanks for your reply.

Kallikuppa Sreenivasa said:
Regarding the signal routing i would recommend following the layout.

I see. Customer will follow Figure 5-1.
TX will be routed on the top layer as same as the SoC.
For RX and CLK, these lines should be routed on the bottom and interior layer, correct?

Thanks and regards,
Koichiro Tashiro

0 Kallikuppa Sreenivasa over 3 years ago in reply to Koichiro Tashiro

TI__Guru**** 192189 points

Hello Koichiro Tashiro,

Thank you for the note.

he planned routing should be fine. Customer should be sure that there is a reference plane available for the signals.

I assume customer would take care of the signal routing related guidelines.

Regards,

Sreenivasa

0 Koichiro Tashiro over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Mastermind 22945 points

Hi Sreenivasa,

Please let me double check what your below comment means.

Kallikuppa Sreenivasa said:
he planned routing should be fine.

Do you mean the customer's original layout (below) should be fine?

Or you meant below updated plan should be fine?

Koichiro Tashiro said:
TX will be routed on the top layer as same as the SoC.
For RX and CLK, these lines should be routed on the bottom and interior layer, correct?

Thanks and regards,
Koichiro Tashiro

0 Kallikuppa Sreenivasa over 3 years ago in reply to Koichiro Tashiro

TI__Guru**** 192189 points

Hello Koichiro Tashiro,

Thank you for checking.

Koichiro Tashiro said:

TX will be routed on the top layer as same as the SoC.
For RX and CLK, these lines should be routed on the bottom and interior layer, correct?

This Should be fine.

Customer should make sure that there is a reference plane available for the routed signals.

Regards,

Sreenivasa

0 Koichiro Tashiro over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Mastermind 22945 points

Hi Sreenivasa,

OK, I understood your recommendation is to route RX and CLK on the bottom or interior layer.
But could you comment on the current customer layout? Is this not good?
Top Layer:

3rd layer:

As you can see, RX and CLK are routed on the top layer (roughly 2/5 length and AC coupling) and remaining 3/5 length is routed on the 3rd layer.
Then there are two VIAs for each line.
If customer moves the AC coupling on the bottom layer, additional VIA is required.

Thanks and regards,
Koichiro Tashiro