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TDA3LX: DDR3 DQ Bit Swapping within a Byte Lane

Andrew Boss32
Prodigy 130 points
Part Number: TDA3LX

Is any of the following permissible with the EMIF:

  • Within a byte, DQ signals can be swapped
  • Bytes can be swapped (all signals DQ, DQS, DM have to be swapped)
  • DQ signal should not be swapped between bytes (e.g. DQ0 going into DQS1 group)
  • 0
    Prodigy 130 points

    Also, is it permissible to swap address lines?

  • 0
    TI__Mastermind 35250 points

    Hi Andrew,

    Yes, when TDA3x is interfaced to DDR3:

    • The DQ signals within a byte lane can be swapped 
    • All signals within a byte lane can be swapped with another byte lane (note that we support interfacing to 4x distinct 8-bit width DDR3 memories, where the concept of swapping byte lanes would not apply)
    • DQ signals should not be swapped between byte lanes

    I do not think the address pins (A15:0) or bank address pins (BA2:0) can be swapped. I believe these are used to program the DDR3 mode registers (inside the DRAM), and there is no way to re-map the address pin to function inside the TDA3x controller.

    Regards,
    Kevin