TMS320C6657: About ROM Bootloader and Secondary bootloader

yoonseok shim

Intellectual 800 points

Part Number: TMS320C6657

Hi TI,

1. I am confused whether ROM bootloader and Secondary bootloader are same or not.

if not, is ROM bootloader called Primary bootloader?

the descriptions below are what I have learned from Technical Reference manual.

The ROM Boot Loader (RBL) is software code that resides in the on-chip read only memory (ROM) to assist the customer in transferring and executing their application code. The start address of the RBL is 0x20B00000.

and what I have learned about RBL is that It initiates initialization in a boot process selected by boot configuration pin and DEVSTAT register.

and It seems to be possible for RBL to load boot table of a app to a SRAM without the help of secondary bootloader....

2. Is there any doc having descriptions of secondary bootloader and its relationship with ROM bootloader?

3. If it is correct that secondary bootloader is called by ROM bootloader, how does it do? is there any doc for explaining it?

4. and i'd like to know the TI example code that write secondary bootloader or application binary or hex images to NOR FLASH.

and

5. the sequence of the program execution on both core0 and core1.

- All I know is that core0 can initiates the execution of a application on core1. how?

please guide me to the thread that have explanation about it.

Regards,

ysshim

over 3 years ago

+1 Shankari G over 3 years ago

TI__Mastermind 25535 points

yyshim,

Good day.

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Question 1

1. I am confused whether ROM bootloader and Secondary bootloader are same or not.

if not, is ROM bootloader called Primary bootloader?

Answer :

ROM bootloader is the primary boot loader. RBL stands for "ROM-BOOT-Loader"

Secondary bootloader is different. For example, IBL is the secondary bootloder. IBL stands for "Intermediate Bootloader".

For RBL features, please refer to : https://www.ti.com/lit/ug/sprugy5c/sprugy5c.pdf

Additionally, For C6657, please refer to https://www.ti.com/lit/ds/symlink/tms320c6657.pdf page no : 168

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software driven, using the BOOTMODE[2:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes: • ROM Boot - C66x CorePac0 is released from reset and begins executing from the L3 ROM base address. After performing the boot process (for example, from I 2C ROM, Ethernet, or RapidIO), C66x CorePac0 then begins execution from the provided boot entry point. For C6657 only, the other C66x CorePac is released from reset and begins executing an IDLE from the L3 ROM. It is then released from IDLE based on interrupts generated by C66x CorePac0. See the Bootloader for the C66x DSP User's Guide for more details. The boot process performed by the C66x CorePac0 in ROM boot is determined by the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the associated boot process in software. Figure 6-26 shows the bits associated with BOOTMODE[12:0].

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Question 2:

2. Is there any doc having descriptions of secondary bootloader and its relationship with ROM bootloader?

Answer : Yes it there. https://www.ti.com/lit/ug/sprugy5c/sprugy5c.pdf ( page no : 35 )

When we do POR - power on reset, RBL is the one which gets executed first and then the IBL and then the app code.

Even without IBL also, it is possible to just have RBL and then the app code. IBl will be flashed into EEPROM. And the app code shall be in SPI-NOR or NAND.

Please refer to the different boot scenarios explained here : https://www.ti.com/lit/ug/sprugy5c/sprugy5c.pdf ( page no; 35 )

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Question 3

3. If it is correct that secondary bootloader is called by ROM bootloader, how does it do? is there any doc for explaining it?

Answer :

For each boot mode, the boot scenerios are explained in https://www.ti.com/lit/ug/sprugy5c/sprugy5c.pdf , starting from page no; 35....

Chapter 3 ---> 3.12 Boot Scenarios

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Question 4

4. and i'd like to know the TI example code that write secondary bootloader or application binary or hex images to NOR FLASH.

Answer:

I have exclusively created a detailed step-by-step-guide for flashing the IBL and booting the app from SPI-NOR.

Here, I have taken uart as an example code for flashing into SPI-NOR.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1057566/faq-tms320c6657-how-to-flash-the-ibl-intermediate-boot-loader-into-eeprom-and-how-to-flash-the-application-binary-into-nor-how-to-boot-the-ibl-application-binary

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Question 5:

5. the sequence of the program execution on both core0 and core1.

Answer:

You mean, how to wake up core 1 from core 0 right ??

I have created another FAQ for this. Please have a look.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1107106/faq-tms320c6657-how-to-wake-the-second-core-by-the-first-core-in-c6657-what-is-boot-magic-address-jump-boot-address

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Regards

Shankari G

0 yoonseok shim over 3 years ago in reply to Shankari G

Intellectual 800 points

Dear Shankari G,

Thasnk you so much for your supports..

I really appreciate it so much my mate!

Regards

ysshim

0 yoonseok shim over 3 years ago in reply to Shankari G

Intellectual 800 points

Dear Shankari G,

Is it available to see IBL source code?

I'd like to see how IBL is programmed with C

Regards,

ysshim

+1 Shankari G over 3 years ago in reply to yoonseok shim

TI__Mastermind 25535 points

ysshim,

Yes, IBL source is available as a part of PDK - Processor SDK 6.3

Location : \ti\pdk_c665x_2_0_16\packages\ti\boot\ibl

Regards

Shankri G

0 yoonseok shim over 3 years ago in reply to Shankari G

Intellectual 800 points

Dear Shankari,

when are 'writing exact data values to kick0 and kick1 registers' required during boot process?

I have checked boot magic address and IPCGRx register are exceptions that are not protected by a kicker

mechanism.

Is it a correct sequence to initiates core 1 to be run by a core 0? Am I understanding correctly?

step 1. Load a app for second core into a FLASH or EEPROM.

step 2. Write entry point of the app aforementioned at step 1 into Boot Magic Address.

step 3. Write 0x01 to IPCGR register.

then core 1 is awaken from IDLE by core 0 and execute the app.

Regards

ysshim

+1 Shankari G over 3 years ago in reply to yoonseok shim

TI__Mastermind 25535 points

ysshim,

yes, that's right.

Regards

Shankari G

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TMS320C6657: About ROM Bootloader and Secondary bootloader