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Two C6678L EVMs communicate in PCIe Asynchronous mode

Nori Shinozaki
Intellectual 2430 points
Other Parts Discussed in Thread: CDCE62005

Hello,

Is it possible for two 6678EVMs to communicate each other with PCIe in asynchronous mode?


PCIe_CLKP is default 100MHz by SW5, how can I change the clock sourced from CDCE62005 to AMC?

Is there any switch on the board?

Regards,
n.Shinozaki

  • 0
    TI__Genius 12065 points

    Hi Nori

    The PCIe supports duplex communication (transmit/receive traffic in both directions at the same time), so I think the two 6678EVM could be working to each other in asynchronous mode.

    According the EVM hardware design team, the clock source switching from clock generator to AMC is a configuration change that requires a soldering iron. So not a simple switch will do the job.

    The changes include: connect PCIE REF CLK (FCLK) from the AMC connector to C6678 DSP on our EVMs by mounting C527 and C528 and by un-mounting C501 and C502. This connects ATX MB PCIE reference clock to C6678.

    Please let me know if you need more information about this.

     

    Sincerely,

    Steven


     

  • 0 in reply to Steven Ji
    TI__Intellectual 2430 points

    Hello Steven,

    Thanks for your answers.

    Let me check on the clocks.

    The "EVM Technical Reference Manual" explains how to set "C66x DSP System PLL Configuration" in "Table 3.16 : SW3-SW6, DSP Configuration Switch".

    1. Which clock in "Figure 2.2: TMDXEVM6678L EVM Clock Domains" is true to this DSP System clock?

    2. If it's CORE_CLKP, does changing the value affect to PRI_REF to the other CDCE6205, PA_SS_CLKP, and PCIe_CLKP?

    In other words, these three clocks will become the same value as CORE_CLKP?

    I mean I would like to keep PCIe_CLKP 100MHz.

    Regards,

    Nori Shinozaki

  • 0 in reply to Nori Shinozaki
    TI__Genius 12065 points

    Hi Nori,

    1. Core_CLK should be the system clock for DSP.

    2. If you take a look at the CDCE62005 data manual, you will find that the each of the 5 outputs (U0~U4) has its own clock divider and those values are independent. They can be configured by the FPGA and EEPROM on the EVM. So changing the value of CORE_CLKP (U3) should not change the value of PRI_REF(U0) and not affecting the other outputs like PA_SS_CLK and PCIe_CLK.

     

    Sincerely,

    Steven

     

  • 0 in reply to Steven Ji
    TI__Intellectual 2430 points

    Steven,

    Thank you!

    Best Regards,

    Nori Shinozaki