I'm trying to understand what options are available for sharing data between PRU cores across a slice (ie sharing the same data between PRU0, PRU1, RTU_PRU0, TX_PRU0, PRU1, RTU_PRU1, and TX_PRU1). This question is general, but the first application will be processing data from multiple ADCs and writing commands to multiple DACs. Since the PRUs are the only cores with access to GPIO, I want to transfer data from PRUs to RTU_PRUs and TX_PRUs for processing, and then write resulting commands back to PRUs. I'm thinking I'll need all 4 aux cores (RTU_PRU0/1 and TX_PRU0/1) for processing the ADC streams and generating the DAC commands, and both PRU cores (in a slice) for reading/writing GPIO to the ADCs and DACs.
We originally planned to share data using DRAM or SRAM, but it appears this incurs arbitration delays if 6 PRU cores are reading or writing the same endpoint at the same time. Since our application is latency-sensitive I'm concerned these delays could be a problem.
Looking for alternatives, it seems AM6442 doesn't include dual-port memories that would allow the PRU cores to avoid arbitration during read/write. Is that correct?
The TRM (rev C) on page 3372 and 3373 indicates that there might be broadside connections to transfer between the various PRU cores (" Broadside (32 Byte) connection to...RTU_PRUm and TX_PRUm (where m = 0 or 1)") but I can't find any broadside IDs for inter-core transfer in Table 6-428 on page 3427. Other comments on the forums suggest that PRUs on AM6442 do not actually have a broadside connections between cores.
The IPC Scratchpad looks like an option, but this scratchpad is small and only supports RTU_PRU, not the TX_PRU.
XFR2VBUS allows access to DDR and other external memories, but we've benchmarked this and the latency is too high for our application.
Are there any options I've missed for sharing data between the various PRU cores that can avoid arbitration delays if all 6 cores in a slice are reading from the same endpoint at the same time?
