Part Number: TDA4VM
Hello,TI
The following parameters are the requirements for eDP parameters:
## Serializer: DS90Ux983-Q1 ## User Inputs: ## Serializer I2C Address= 0x18 ## Max DP Lane Count = 2 ## Max DP Lane Rate = 5.4Gbps ## DPRX no SSC Mode Enabled ## DP SST Mode Enabled ## eDP Mode Enabled ## FPD-Link Configuration: FPD-Link IV Single Port 0 - 3.375Gbps ## Video Processor 0 (Stream 0) Properties: ## Total Horizontal Pixels = 2040 ## Total Vertical Lines = 1114 ## Active Horizontal Pixels = 1920 ## Active Vertical Lines = 1080 ## Horizontal Back Porch = 60 ## Vertical Back Porch = 10 ## Horizontal Sync = 40 ## Vertical Sync = 2 ## Horizontal Front Porch = 20 ## Vertical Front Porch = 22 ## Horizontal Sync Polarity = Positive ## Vertical Sync Polarity = Positive ## Bits per pixel = 24 ## Pixel Clock = 136.36MHz
My modifications in the SDK_8.0 are as follows:
app_init.c:
prm.timings.width = 1920U;
prm.timings.height = 1080U;
prm.timings.hFrontPorch = 20U;
prm.timings.hBackPorch = 60U;
prm.timings.hSyncLen = 40U;
prm.timings.vFrontPorch = 22U;
prm.timings.vBackPorch = 10U;
prm.timings.vSyncLen = 2U;
prm.timings.pixelClock = 136353600ULL;
dss_dctrlExtended.c:
static int32_t Dss_dctrlDrvInitDPTX(uint32_t isHpdSupported){
...
...
pObj->srcCaps.laneCount = 2;
...
..
After this modification, the DP display cannot be output with vx_app_tidl
eDP corresponds to the modification of 2 lanes, is my code correct?
Is there anything missing?
