DDR3 Data Verification failure for Big-Endian mode

Venkat,

1. what is the version of the gel file you used? Yhe version gets printed on the console after you run the *Global_Default_Setup* Gel function. Please send the dump.

2. There is no difference in the Gel for LE and BE versions. So, if everything worked for you under LE, then I expect it should work for BE also.

Can you please make sure the following to make your work transit from LE (working) to BE and let us know the results.

2a. Make sure the Program is compiled for Big Endian Mode.

2b. Make sure the dip switch for C6678L EVM (SW3 pin 1 is set to on - (away from the EVM) for BE mode)

2c. Power cycle the board and make sure you run the *Global Defalt Setup* Gel file.

2d. Load and execute your program.

Let me know if any of the above helps.

-Aravind

Hi Aravind,

I haven't run this GEL function earlier (for both LE and BE loads), but followed and double checked all the steps you mentioned.

After running this GEL also, there is no progress. The BE build is still fails to load the program. I have loaded the gel file came along with the EVM.

Here is the snapshot of console after running this GEL function

C66xx_0: GEL Output: Global Default Setup...

C66xx_0: GEL Output: Setup Silent called...

C66xx_0: GEL Output: Setup Cache... 

C66xx_0: GEL Output: L1P = 32K   

C66xx_0: GEL Output: L1D = 32K   

C66xx_0: GEL Output: L2 = ALL SRAM   

C66xx_0: GEL Output: Setup Cache... Done.

C66xx_0: GEL Output: PLL1 Setup... 

C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.

C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.

C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.

C66xx_0: GEL Output: PLL1 Setup... Done.

C66xx_0: GEL Output: PLL2 Setup... 

C66xx_0: GEL Output: PLL2 Setup for DDR3 @ 666.7 MHz... 

C66xx_0: GEL Output: PLL2 Setup... Done.

C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 

There is no version number printed.

Thanks,

Venkat

Venkat,

I received an internal update regarding a CCS patch with the correct GEL file to be used.

http://processors.wiki.ti.com/index.php/Category:Code_Composer_Studio_v5

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_ccstudio/CCSv5/CCS_5_0_2/exports/extras_patch.zip

Arvind:Please add any further comments.

Naga,

Thanks for providing the link for the updated Gel file. I was about to do the same thing.

Venkat,

Yes, the very early version of the gel file (that you are using now) did not have the version string getting printed. This is what I wanted to know.

Please use the evmc6678l.gel file (version 1.4) from the above link and let me know if it helps.

We fixed few initialization sequence for the DDR3 in the gel file. (Make sure the version printed is 1.4 for the gel file)

-Thanks,
Aravind

Naga/Aravind,

Thanks for your support.

With the new GEL file, I could able to load the program onto C66x target with code placed in DDR3. However, My code is now going infinite. Now this behavior is same for both BE and LE. It was observed that CPU is waiting for PLL setting to happen.

The following is printed on console when I run the GEL function Global_Default_Setup

C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: C6678L GEL file Ver is 1.4
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K  
C66xx_0: GEL Output: L1D = 32K  
C66xx_0: GEL Output: L2 = ALL SRAM  
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: PLL1 Setup...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL is using SYSCLK/ALTCORECLK as the input
C66xx_0: GEL Output: PA PLL is in PLL mode
C66xx_0: GEL Output: PA PLL fixed output divider = 2
C66xx_0: GEL Output: PA PLL programmable multiplier = 21
C66xx_0: GEL Output: PA PLL programmable divider = 1
C66xx_0: GEL Output: the output frequency should be 10 times the PA reference clock
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output:
SGMII SERDES has been configured.
C66xx_0: GEL Output: Enabling EDC ...
C66xx_0: GEL Output: L1P error detection logic is enabled.
C66xx_0: GEL Output: L2 error detection/correction logic is enabled.
C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_0: GEL Output: Enabling EDC ...Done
C66xx_0: GEL Output: Configuring CPSW ...
C66xx_0: GEL Output: Configuring CPSW ...Done
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: Global Default Setup... Done.

I observed some TIMEOUT ERROR above, Does it have any impact on my code.

I was trying to run the example code provided along with EVM "mcsdk_2_00_00_beta1\examples\ndk\evmc6678l\helloWorld"

Thanks,

Venkat

Venkat,

Wow - good to know that it worked for you.

C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!  is perfectly fine output - This indicates the gel timed out while enabling power domain 2 and module 9 - which is for Security (please refer to Power Sleep controller user manual for details - the link is provided in the tms320C6678 data sheet).

Regarding running the helloworld/Client examples please refer to \ndk_2_20_03_24\packages\ti\ndk\docs\stack\spru523_ug.pdf

-Best Regards,

Aravind

Arvind,

Why does the SA time out when turning its clock domain on? I have searched the both the PSC document and found no specific reference to that issue. Is this feature restricted in some devices?

Yishay