AM5716: Current Program Status Register (CPSR) I bit set up for CPU IDEL test

Hi Kuerbis,

Kuerbis said:

my customer is trying CPU IDEL test under PDK ti/drv/pm/examples/cpuidle/main_a15.c.

Were they able to enter idle mode?

Kuerbis said:

But CPU never wake up by an interrupt of timer4 after it.

Also, have you verified that interrupt itself is getting generated?

Regards,
Parth

HI Parth,

> Were they able to enter idle mode?

It seems they couldn't enter idle mode based on status register and power measurement.

>Also, have you verified that interrupt itself is getting generated?

Which the register bit should we check?

They wants to know What value should they set CPSR.I bit for CPU IDEL test.  Should it be enable? 

Thanks and Best regards,

 Kuerbis

Hi  Kuerbis,

I checked, CPSR.I bit is set to 0 before WFI is executed while running CPU_IDLE test.

Regards,
Parth