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TDA4VM: J721S2 uboot r5 sf probe indirect_read stuck

Part Number: TDA4VM

Hi expers,

I try to boot from spi nor flash (ospi1), the rom code load tiboot3.bin from nor flash success but  uboot r5 spl run sf probe got stuck while read sfdp.

spi_nor_scan->

spi_nor_init_params->

spi_nor_parse_sfdp->

spi_nor_read_sfdp->

...

cadence_qspi_apb_indirect_read_execute

static int
cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
				       unsigned int n_rx, u8 *rxbuf)
{
	unsigned int remaining = n_rx;
	unsigned int bytes_to_read = 0;
	int ret;

	writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);

	/* Start the indirect read transfer */
	writel(CQSPI_REG_INDIRECTRD_START,
	       plat->regbase + CQSPI_REG_INDIRECTRD);

	while (remaining > 0) {
		ret = cadence_qspi_wait_for_data(plat);
		if (ret < 0) {
			printf("Indirect write timed out (%i)\n", ret);
			goto failrd;
		}

		bytes_to_read = ret;

		while (bytes_to_read != 0) {
			bytes_to_read *= plat->fifo_width;
			bytes_to_read = bytes_to_read > remaining ?
					remaining : bytes_to_read;
			/*
			 * Handle non-4-byte aligned access to avoid
			 * data abort.
			 */
			if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
				readsb(plat->ahbbase, rxbuf, bytes_to_read);
			else
				readsl(plat->ahbbase, rxbuf,
				       bytes_to_read >> 2);
			rxbuf += bytes_to_read;
			remaining -= bytes_to_read;
			bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
		}

	}

the vaule of bytes_to_read always 16.

But the nor flash access is normal on uboot-a72.

Can you provide some suggestions (sdk ti-processor-sdk-linux-j721s2-evm-08_00_04_05)?

Regards,

Li quan

  • Hello Li Quan,

    xSPI Boot:

    Flashing instructions from mmc-SD to xSPI:

    sf probe
    fatload mmc 1 ${loadaddr} tiboot3.bin; sf update $loadaddr 0x0 $filesize;
    fatload mmc 1 ${loadaddr} tispl.bin; sf update $loadaddr 0x80000 $filesize;
    fatload mmc 1 ${loadaddr} u-boot.img; sf update $loadaddr 0x280000 $filesize
    


    Power off & change dip switch settings to below;

    SW8: 00001010
    SW9: 01100000

    U-Boot logs:

    U-Boot SPL 2021.01-g139f16e4c6 (Dec 09 2021 - 16:27:18 +0000)
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.9.0--w2021.33-j721s2 (Terrif')
    SPL initial stack usage: 13440 bytes
    Trying to boot from SPI
    Starting ATF on ARM64 core...

    NOTICE:  BL31: v2.5(release):08.00.00.004-dirty
    NOTICE:  BL31: Built : 16:15:40, Dec  9 2021

    U-Boot SPL 2021.01-g139f16e4c6 (Dec 09 2021 - 16:23:11 +0000)
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.9.0--w2021.33-j721s2 (Terrif')
    Trying to boot from SPI
    cadence_spi spi@47040000: Can't get reset: -2
    jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
    k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:272
    k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled

    U-Boot 2021.01-g139f16e4c6 (Dec 09 2021 - 16:23:11 +0000)

    SoC:   J721S2 SR1.0
    Model: Texas Instruments J721S2 EVM
    ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
    ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
    Board: J721S2X-PM1-SOM rev E1
    DRAM:  16 GiB
    Flash: 0 Bytes
    MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
    Loading Environment from MMC... OK
    In:    serial@2880000
    Out:   serial@2880000
    Err:   serial@2880000
    Net:   am65_cpsw_nuss_slave ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
    eth1: ethernet@46000000
    Hit any key to stop autoboot:  0

    xSPI boot is supported. Can you confirm that xSPI boot is working for you?
    - Keertthy