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suspend Successfully But wakeup immediately.

teddy stone
Intellectual 520 points
Other Parts Discussed in Thread: TPS65930, DM3730

We are working on getting our system (OMAP3730 and TPS65930) to sleep and wakeup.

Using the information on http://elinux.org/OMAP_Power_Management,

and I have gone through the web page http://processors.wiki.ti.com/index.php/OMAP35x_Debug_Steps_for_Idle_Entry 

 

I do the following sequences to test sleep and wakeup:

1.

echo 1 > /debug/pm_debug/sleep_while_idle

echo 1 > /debug/pm_debug/enable_off_mode

echo 1 > /debug/pm_debug/voltage_off_while_idle

2.

echo mem > /sys/power/state

 

3.

Now it can show "Successfully put all powerdomains to target state " ,But resume immediately, the wakeup debug message is "WAKEUP BY: PRM_IRQSTATUS(0x8004c10)".

 

************

My question:

************

Does the information above can indicate that it got to the OFF state? 

If so, why does it wakeup?

How could i diagnose this issue?

 

 

Below is more debug informations :

-------------------------------------------------------

/sys/kernel/debug/pm_debug # cat count 

usbhost_pwrdm (ON),OFF:1,RET:0,INA:0,ON:2

sgx_pwrdm (OFF),OFF:19,RET:0,INA:0,ON:19

per_pwrdm (ON),OFF:1,RET:2830,INA:0,ON:2832

dss_pwrdm (ON),OFF:1,RET:0,INA:0,ON:2

cam_pwrdm (OFF),OFF:1,RET:2,INA:0,ON:2

core_pwrdm (ON),OFF:1,RET:0,INA:0,ON:2

neon_pwrdm (ON),OFF:1,RET:2811,INA:28,ON:2841

mpu_pwrdm (ON),OFF:1,RET:2811,INA:28,ON:2841

iva2_pwrdm (OFF),OFF:1,RET:1,INA:0,ON:1

per_clkdm->per_pwrdm (9)

usbhost_clkdm->usbhost_pwrdm (3)

cam_clkdm->cam_pwrdm (0)

dss_clkdm->dss_pwrdm (3)

core_l4_clkdm->core_pwrdm (9)

core_l3_clkdm->core_pwrdm (5)

d2d_clkdm->core_pwrdm (0)

sgx_clkdm->sgx_pwrdm (0)

iva2_clkdm->iva2_pwrdm (0)

neon_clkdm->neon_pwrdm (0)

mpu_clkdm->mpu_pwrdm (0)

prm_clkdm->wkup_pwrdm (0)

cm_clkdm->core_pwrdm (0)

-------------------------------------------------------

 

It's sound that all the power domain got to the off state once when system sleep.

But when I check the dump register in /sys/kernel/debug/pm_debug/registers/1 as below command:

/sys/kernel/debug/pm_debug/registers # cat 1

 

In http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/77848/278434.aspx#278434, [Kazunobu Shin] provided a PRCM register snapshot taken just before  a successful suspend,

After compare mine with this example , and lookup to DM3730's datasheet, I find that all the CM module registers are porper,But the PRM module registers are not OK:the RM_RSTST_XXX is not clear to 0. Below is the detail

-------------------------------------------------------

MOD: PRM_MPU (48306900)

  58 => 0000000c = 0b1100

bit3:Read 0x1: MPU domain has been reset following a CORE power domain wake-up from OFF to ON.

bit2:Read 0x1: MPU domain has been reset following a MPU power domain wake-up.

 

MOD: PRM_CORE (48306a00)

  58 => 00000304 = 0b0100

bit2: Read 0x1: CORE domain has been reset following a CORE power domain wake-up.

 

MOD: PRM_SGX (48306b00)

  58 => 0000000d = 0b1101

  bit3:Read 0x1: SGX domain has been reset following a CORE power domain wake-up from OFF to ON.

  bit2:Read 0x1: SGX domain has been reset following a SGX domain wake-up.

  bit0:Read 0x1: SGX domain has been reset upon a global cold reset

 

MOD: PRM_DSS (48306e00)

  58 => 0000000c = 0b1100

bit3:Read 0x1: DSS domain has been reset following a CORE power domain wake-up from OFF to ON.

bit2:Read 0x1: DSS domain has been reset following a DSS power domain wake-up.

 

MOD: PRM_CAM (48306f00)

  58 => 00000001 = 0b0001

bit0:Read 0x1: CAM domain has been reset upon a global cold reset

 

MOD: PRM_PER (48307000)

  58 => 0000000c = 0b1100

bit3:Read 0x1: PER domain has been reset following a CORE power domain wake-up from OFF to ON.

bit2:Read 0x1: PER domain has been reset following a PERIPHERAL power domain wake-up.

 

 

MOD: PRM_EMU (48307100)

  58 => 00000004 = 0b0100

bit2:Read 0x1: EMULATION domain has been reset following an EMULATION power domain wake-up.

 

MOD: PRM_NEON (48307300)

  58 => 0000000c = 0b1100

bit3:Read 0x1: NEON domain has been reset following a CORE power domain wake-up from OFF to ON.

bit2:Read 0x1: NEON domain has been reset following a NEON power domain wake-up.

 

MOD: PRM_USB (48307400)

  58 => 0000000c = 0b1100

bit3:Read 0x1: USB HOST domain has been reset following a CORE power domain wake-up from OFF to ON.

bit2:Read 0x1: USB HOST domain has been reset following an USB HOST power domain wake-up.  

-------------------------------------------------------

Please give some suggestion to me, any suggestion is useful to me.

thanks for any assistance!

  • 0
    Intellectual 520 points

    when i set CM_AUTOIDLE_PLL bit[5:3] to 0,(set AUTO_PERIPH_DPLL automatically control disable),suspend and resume is work properly.But when i check the registers,I find that the DPLL4 is still locked.

    (If we set CM_AUTOIDLE_PLL bit[5:3] to 0,DPLL4 is automatically put in low power state when suspend.)

     

    And now the  RM_RSTST_XXX is:

    MOD: PRM_SGX (48306b00)

      58 => 00000005 = 0b0101

    bit2:Read 0x1: SGX domain has been reset following a SGX domain wake-up.

    bit0:Read 0x1: SGX domain has been reset upon a global cold reset

     

    MOD: PRM_CAM (48306f00)

      58 => 00000001 = 0b0001

    bit0:Read 0x1: CAM domain has been reset upon a global cold reset

     

    what does it mean? 

    Any suggestion is useful.

    Thank you very much!

     

  • 0 in reply to teddy stone
    Intellectual 520 points

    Any  one can help me?

    Thanks ! 

  • 0 in reply to teddy stone
    TI__Genius 16690 points

    Can you dump PRCM registers by cat /debug/pm_debug/registers/2 after wake-up and review below PM_PREPWSTST values ? PM_PREPWSTST values tell you what was power domain status during suspend if you dump these values after wake-up.  

    • PM_PREPWSTST_MPU: The MPU power domain previous power state status

    • PM_PREPWSTST_CORE: The CORE power domain previous power state status

    • PM_PREPWSTST_SGX: The SGX power domain previous power state status

    • PM_PREPWSTST_DSS: The DSS power domain previous power state status

    • PM_PREPWSTST_CAM: The CAM power domain previous power state status

    • PM_PREPWSTST_PER: The PER power domain previous power state status

    • PM_PREPWSTST_NEON: The NEON power domain previous power state status

    • PM_PREPWSTST_IVA2: The IVA2 power domain previous power state status

    • PM_ PREPWSTST_USBHOST: The USBHOST power domain previous power state status

    Can you try suspend w/o voltage_off_while_idle option ? I'm not sure that this option really works.

  • 0 in reply to kshin
    Intellectual 520 points

    Thank you very much for your advice.

     I dumped the registers by "cat /debug/pm_debug/registers/2  " after wake-up, and the PM_PREPWSTST of all the power domain are  set to 0

    Does it mean that all the power domain  entered off mode before wake-up?

    I try to set  voltage_off_while_idle to 0 and 1, and the result is not different.

     

    below is my registers dump:

    /sys/kernel/debug/pm_debug/registers # cat 1

    MOD: CM_IVA2 (48014000)

      04 => 00000017  20 => 00000001  34 => 00000001  40 => 00080a00

      44 => 00000001  48 => 00000003

    MOD: CM_OCP (48004800)

      00 => 00000010  10 => 00000001

    MOD: CM_MPU (48004900)

      04 => 00000037  24 => 00000001  34 => 00000001  40 => 0010960c

      44 => 00000001  48 => 00000003  4c => 00000001

    MOD: CM_CORE (48004a00)

      10 => 00000042  20 => ffffffbd  24 => 0000001f  28 => 0000000d

      30 => fffffed9  34 => 0000001f  38 => 0000000c  40 => 0000130a

      48 => 0000003f  4c => 00000003

    MOD: CM_SGX (48004b00)

      20 => 00000001  40 => 00000005  48 => 00000003

    MOD: CM_WKUP (48004c00)

      00 => 00000001  10 => 0000000d  20 => 000002f2  30 => 0000003f

      40 => 00000014

    MOD: CM_CCR (48004d00)

      00 => d8371007  04 => 00000011  20 => 00000001  30 => 00000009

      34 => 00000001  40 => 08c80c00  44 => 0481b00c  48 => 00000009

      4c => 00003c0c  50 => 00000001  70 => 00000003

    MOD: CM_DSS (48004e00)

      20 => 00000003  30 => 00000001  40 => 0000100c  48 => 00000003

    MOD: CM_CAM (48004f00)

      20 => 00000001  30 => 00000001  40 => 00000004  48 => 00000003

    MOD: CM_PER (48005000)

      10 => 0003e000  20 => 00041fff  30 => 0003ffff  40 => 000000ff

      44 => 00000006  48 => 00000003  4c => 00000001

    MOD: CM_EMU (48005100)

      40 => 03020a50  48 => 00000002  4c => 00000001

    MOD: CM_NEON (48005300)

      48 => 00000003

    MOD: CM_USB (48005400)

      20 => 00000003  30 => 00000001  48 => 00000003

    MOD: PRM_IVA2 (48316000)

      50 => 00000007  e0 => 00ff0f04  f8 => 00000002

    MOD: PRM_OCP (48306800)

      04 => 00000010  14 => 00000001  18 => 08004c10  1c => 00000201

    MOD: PRM_MPU (48306900)

      58 => 0000000c  d4 => 00000012  e0 => 00030104  e4 => 000000c7

      e8 => 000000c7

    MOD: PRM_CORE (48306a00)

      58 => 00000304  a0 => c33ffe18  a4 => c33ffe18  e0 => 000f0314

      e4 => 000000f7  e8 => 000000f7  f0 => 00000004  f8 => 00000004

    MOD: PRM_SGX (48306b00)

      58 => 0000000d  e0 => 00030104

    MOD: PRM_WKUP (48306c00)

      a0 => 0001010b  a4 => 0000010b

    MOD: PRM_CCR (48306d00)

      40 => 00000003

    MOD: PRM_DSS (48306e00)

      58 => 0000000c  a0 => 00000001  e0 => 00030104

    MOD: PRM_CAM (48306f00)

      58 => 00000001  e0 => 00030104

    MOD: PRM_PER (48307000)

      58 => 0000000c  a0 => 0003e807  a4 => 0003e807  c8 => 00000007

      e0 => 00030104  e4 => 00000007  e8 => 00000007

    MOD: PRM_EMU (48307100)

      58 => 00000004  e4 => 00000103

    MOD: PRM_GLBL (48307200)

      20 => 00120012  24 => 00010000  2c => 17201e00  30 => 23201e00

      34 => 00120000  38 => 00000018  54 => 00001006  58 => 00000001

      60 => 0000000c  64 => 00000050  70 => 00000048  90 => 0fff0fff

      94 => 000000ff  98 => 000000ff  9c => 00000002  a0 => 000000ff

      b0 => 000c1708  b4 => 00003c01  b8 => 00003c04  bc => 4414ffff

      c0 => 00000017  c4 => 00000001  d0 => 00162308  d4 => 00003c01

      d8 => 00003c04  dc => 4218ffff  e0 => 00000023  e4 => 00000001

    MOD: PRM_NEON (48307300)

      58 => 0000000c  c8 => 00000002  e0 => 00000004  e4 => 00000003

      e8 => 00000003

    MOD: PRM_USB (48307400)

      58 => 0000000c  a0 => 00000001  a4 => 00000001  a8 => 00000001

      e0 => 00030114

    ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    /sys/kernel/debug/pm_debug/registers # cat 2
    MOD: CM_IVA2 (48014000)
      04 => 00000011  20 => 00000001  40 => 00080000  44 => 00000001
    MOD: CM_OCP (48004800)
      00 => 00000010  10 => 00000001
    MOD: CM_MPU (48004900)
      04 => 00000037  24 => 00000001  34 => 00000001  40 => 0010960c
      44 => 00000001  4c => 00000001
    MOD: CM_CORE (48004a00)
      10 => 0000004a  20 => ffffffbd  24 => 0000001f  28 => 0000000d
      30 => 00000008  40 => 0000130a  4c => 00000003
    MOD: CM_SGX (48004b00)
      20 => 00000001
    MOD: CM_WKUP (48004c00)
      20 => 000002ff  40 => 00000014
    MOD: CM_CCR (48004d00)
      00 => d0371007  04 => 00000011  20 => 00000001  30 => 00000009
      40 => 08c80c00  44 => 0481b00c  48 => 00000009  50 => 00000001
      70 => 00000003
    MOD: CM_DSS (48004e00)
      20 => 00000003  40 => 00000404
    MOD: CM_CAM (48004f00)
      20 => 00000001  40 => 00000004
    MOD: CM_PER (48005000)
      20 => 0007ffff  4c => 00000001
    MOD: CM_EMU (48005100)
      40 => 04040a50  48 => 00000002  4c => 00000001
    MOD: CM_NEON (48005300)
    MOD: CM_USB (48005400)
      20 => 00000003
    MOD: PRM_IVA2 (48316000)
      50 => 00000007  e0 => 00ff0f04  f8 => 00000002
    MOD: PRM_OCP (48306800)
      04 => 00000010  14 => 00000001  18 => 08004c10  1c => 00000201
    MOD: PRM_MPU (48306900)
      58 => 0000000c  d4 => 00000012  e0 => 00030104  e4 => 000000c7
    MOD: PRM_CORE (48306a00)
      58 => 00000304  a0 => c33ffe18  a4 => c33ffe18  e0 => 000f0314
      e4 => 000000f7  f0 => 00000004  f8 => 00000004
    MOD: PRM_SGX (48306b00)
      58 => 0000000d  e0 => 00030104
    MOD: PRM_WKUP (48306c00)
      a0 => 0000010b  a4 => 0000010b
    MOD: PRM_CCR (48306d00)
      40 => 00000003
    MOD: PRM_DSS (48306e00)
      58 => 0000000c  a0 => 00000001  e0 => 00030104
    MOD: PRM_CAM (48306f00)
      58 => 00000001  e0 => 00030104
    MOD: PRM_PER (48307000)
      58 => 0000000c  a0 => 0003e807  a4 => 0003e807  c8 => 00000007
      e0 => 00030104  e4 => 00000007
    MOD: PRM_EMU (48307100)
      58 => 00000004  e4 => 00000103
    MOD: PRM_GLBL (48307200)
      20 => 00120012  24 => 00010000  2c => 17201e00  30 => 23201e00
      34 => 00120000  38 => 00000018  54 => 00001006  58 => 00000001
      60 => 0000000c  64 => 00000050  70 => 00000048  90 => 0fff0fff
      94 => 000000ff  98 => 000000ff  9c => 00000002  a0 => 000000ff
      b0 => 000c1708  b4 => 00003c01  b8 => 00003c04  bc => 4414ffff
      c0 => 00000017  c4 => 00000001  d0 => 00162308  d4 => 00003c01
      d8 => 00003c04  dc => 4218ffff  e0 => 00000023  e4 => 00000001
    MOD: PRM_NEON (48307300)
      58 => 0000000c  c8 => 00000002  e0 => 00000004  e4 => 00000003
    MOD: PRM_USB (48307400)
      58 => 0000000c  a0 => 00000001  a4 => 00000001  a8 => 00000001
      e0 => 00030114

  • 0 in reply to teddy stone
    TI__Genius 16690 points

    teddy stone said:
    Does it mean that all the power domain  entered off mode before wake-up?

    Yes. As you mentioned, it looks the processor goes into the OFF mode, but immediately wakes up. I've also reviewed wake-up status registers described in 3.6.2.5.2 PM_WKST_ domain_name (Wake-Up Status Register) in the TRM but couldn't find anything significant. 

    Can you check all wake-up event status and interrupt status after wake-up and see what was the event woke up the processor ? 

  • 0 in reply to kshin
    Intellectual 520 points

     

    we dump the registers  after resume, (by dump_mod_wkst_reg()) , and the result is below:

    WAKEUP BY: WKUP(0x0) CORE1(0x0) CORE3(0x0) PER(0x0) USBHOST(0x0) PRM_IRQSTATUS(0x8004c10) INTC_IRQ0(0x0) INTC_IRQ1(0x0) INTC_IRQ2(0x0) 

     

    It sounds that we can't find out what the wakeup event. Is it right? 

     

    Thank you very much .