TDA4VM: TDA4 isn't update sgmii link status in the initialization phase

Linda Wang

Prodigy 110 points

Part Number: TDA4VM

Hi, engineers of TI,

Some times , we got eth0 mount fail, then we checked mcu2_0 log, we can see program hangs down below:

Then we checked the sgmii register status ，we got 0x00000030

After that, we checked PHY link status, and it is link up!

TDA4 isn't update sgmii link status in the initialization phase, please help us to check how dose it happend.

Thanks a lot.

over 3 years ago

0 Tanmay Patil over 3 years ago

TI__Mastermind 38540 points

Hi Linda,

Can you provide the following clarification :

Linda Wang said:
After that, we checked PHY link status, and it is link up!

By this do you mean the link-status register in the phy's register space or the phy-link status register in CPSW_MDIO registers (0x0C000F0C)?
Which SDK are you you using?
What is the frequency of the issue?
Are their any changes in ethfw for this?

A suggestion : Can you try adding a small sleep (~10us) to the while loop.

Regards,
Tanmay

0 Linda Wang over 3 years ago

Prodigy 110 points

Hi, Tanmay,

1.I mean the link-status register in the phy's register is link up,but in CPSW_MDIO registers I got link down.

2.We use SDK7.2.

3.The frequency is so high, like up to 80% in some specific TDA4, but other TDA4 dosen't appear.

4.There aren't any changes in ethfw for this.

And I will try your suggestion later.

Thanks

0 Tanmay Patil over 3 years ago

TI__Mastermind 38540 points

Hi Linda,

Are you using any HLOS along with ethfw? Is it Linux or QNX?
The eth0 interface corresponds to MCU_CPSW2G, whose driver sits in linux kernel. So, can you clarify what you mean by "eth0 mount fail"

Linda Wang said:
The frequency is so high, like up to 80% in some specific TDA4, but other TDA4 dosen't appear.

If you are talking about different hardware boards, then it is highly likely that the issue could be hardware related.

Are you using the TDA4VM EVM or is it a custom board?
Which CPSW port are you using for the SGMII link? Can you send me your serdes configuration?
What is the phy you are using? Is it etched on the board or is it a separate daughter card? If its a daughter card, it also could be a issue in the connectors.

Linda Wang said:
I mean the link-status register in the phy's register is link up,but in CPSW_MDIO registers I got link down.

The link down in CPSW_MDIO registers would indicate that your phy isn't getting detected. Can you see if the register is "ALIVE". It is indicated in CPSW_MDIO_ALIVE_REG (0x0C000F08)

Regards,
Tanmay

0 Linda Wang over 3 years ago

Prodigy 110 points

Hi, Tanmay,

1. We use linux.

2. We use CPSW9G as the driver, if the ETHFW is finish configuration, on the linux side will mount an eth0 network card like this

but we just get this when the sgmii link status gose wrong.

3.We use CPSW9G port0 for the SGMII link.I can send you c file of serdes configuration,do you have any tools for dump?

4. We use MARVELL 88Q5072, anfd it is etched on the board.

5. Dump register MDIO ALIVE: 0x98000FFF

0 Tanmay Patil over 3 years ago

TI__Mastermind 38540 points

Hi Linda,

Can you post the ethfw logs here.

The serdes configuration would also be helpful.

Regards,
Tanmay

0 Linda Wang over 3 years ago

Prodigy 110 points

Hi, Tanmay,

I dump sgmii register and send Email to Sikai, he will send it to you.

Thanks

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Dear Tanmay,

Sorry I click the "TI think resolved" option by mistake.

Here is their "C" code and ethfw log:

Fullscreen 6443.board_serdes_cfg.c Download

/******************************************************************************
 * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
/**
 *  \file   board_cfg.c
 *
 *  \brief  EVM serdes configuration file
 *
 *  Configures the serdes module.
 *
 */

#include "board_serdes_cfg.h"

static Board_STATUS Board_CfgSgmii(void)
{
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams  = {0};

    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));

    /* SGMII Config */
    serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_SIERRA_SERDES0;
    serdesLane0EnableParams.baseAddr          = CSL_SERDES_16G0_BASE;
    serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane0EnableParams.numLanes          = 0x2;
    serdesLane0EnableParams.laneMask          = 0x3;
    serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;

    serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

    serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

    CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane0EnableParams.phyType,
                       serdesLane0EnableParams.phyInstanceNum,
                       serdesLane0EnableParams.serdesInstance,
                       0U);


    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane0EnableParams.baseAddr,
                                 serdesLane0EnableParams.refClock,
                                 serdesLane0EnableParams.refClkSrc,
                                 serdesLane0EnableParams.serdesInstance,
                                 serdesLane0EnableParams.phyType);

    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }
    /* Assert PHY reset and disable all lanes */
    CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes,
                                 serdesLane0EnableParams.laneMask);

    /* Load the Serdes Config File */
    result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
    /* Return error if input params are invalid */
    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
    if (laneRetVal != 0)
    {
        return BOARD_FAIL;
    }

    return BOARD_SOK;
}

static Board_STATUS Board_CfgQsgmii(void)
{
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams  = {0};

    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));

    /* QSGMII Config */
    serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)SGMII_SERDES_INSTANCE;
    serdesLane0EnableParams.baseAddr          = CSL_SERDES_16G0_BASE;
    serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_5G;
    serdesLane0EnableParams.numLanes          = 0x2;
    serdesLane0EnableParams.laneMask          = 0x3;
    serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_QSGMII;
    serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN4;

    serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

    serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

    CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane0EnableParams.phyType,
                       serdesLane0EnableParams.phyInstanceNum,
                       serdesLane0EnableParams.serdesInstance,
                       SGMII_LANE_NUM);


    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane0EnableParams.baseAddr,
                                 serdesLane0EnableParams.refClock,
                                 serdesLane0EnableParams.refClkSrc,
                                 serdesLane0EnableParams.serdesInstance,
                                 serdesLane0EnableParams.phyType);

    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }
    /* Assert PHY reset and disable all lanes */
    CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes,
                                 serdesLane0EnableParams.laneMask);

    /* Load the Serdes Config File */
    result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
    /* Return error if input params are invalid */
    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
    if (laneRetVal != 0)
    {
        return BOARD_FAIL;
    }

    return BOARD_SOK;
}

/**
 *  \brief serdes configurations
 *
 *  The function configures the serdes1 module for one lane pcie interface
 *
 *  \return   BOARD_SOK in case of success or appropriate error code
 *
 */
Board_STATUS Board_serdesCfgSgmii(void)
{
    Board_STATUS ret;

    /* SERDES0 Initializations */
    ret = Board_CfgSgmii();
    if (ret != BOARD_SOK)
    {
        return ret;
    }

    return BOARD_SOK;
}

/**
 *  \brief serdes configurations
 *
 *  The function configures the serdes1 module for one lane pcie interface
 *
 *  \return   BOARD_SOK in case of success or appropriate error code
 *
 */
Board_STATUS Board_serdesCfgQsgmii(void)
{
    Board_STATUS ret;

    /* SERDES0 Initializations */
    ret = Board_CfgQsgmii();
    if (ret != BOARD_SOK)
    {
        return ret;
    }

    return BOARD_SOK;
}

Fullscreen vx.log Download

root@sixi_master:~# 
root@sixi_master:~# vx_app_linux_arm_remote_log.out 
[MCU2_0]      3.402606 s: CIO: Init ... Done !!!
[MCU2_0]      3.402673 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_0]      3.402714 s: APP: Init ... !!!
[MCU2_0]      3.402733 s: SCICLIENT: Init ... !!!
[MCU2_0]      3.403058 s: SCICLIENT: DMSC FW version [20.8.7--v2020.08d (Terrific Lla]
[MCU2_0]      3.403092 s: SCICLIENT: DMSC FW revision 0x14  
[MCU2_0]      3.403115 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      3.403137 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      3.403158 s: UDMA: Init ... !!!
[MCU2_0]      3.405328 s: UDMA: Init ... Done !!!
[MCU2_0]      3.405380 s: MEM: Init ... !!!
[MCU2_0]      3.405415 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!!
[MCU2_0]      3.405469 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
[MCU2_0]      3.405517 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ 94000000 of size 65536 bytes !!!
[MCU2_0]      3.405560 s: MEM: Init ... Done !!!
[MCU2_0]      3.405579 s: IPC: Init ... !!!
[MCU2_0]      3.405605 s: IPC: 7 CPUs participating in IPC !!!
[MCU2_0]      3.405636 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]      3.405662 s: IPC: HLOS is ready !!!
[MCU2_0]      3.413359 s: IPC: Init ... Done !!!
[MCU2_0]      3.413429 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]      3.414321 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]      3.414375 s: ETHFW: Init ... !!!
[MCU2_0]      3.415922 s: ==get_project_id_for_eth: get_acu_project_id:2 ==
[MCU2_0]      3.415984 s: ETHFW INIT: ==============================================Total ports:2
[MCU2_0]      3.416303 s: CPSW_9G Test on MAIN NAVSS
[MCU2_0]      3.427837 s: EnetBoard_setPhyConfig: WLY TEST >>>> EnetBoard_setPhyConfig start. 6
[MCU2_0]      3.427899 s: EnetBoard_setPhyConfig: V1/enet_appboardutils_j721e_evm.c 833, EnetBoard_setPhyConfigSgmii portNum 0
[MCU2_0]      3.463727 s: Cpsw_openPortLinkAndPhy: WLY TEST>>>>>>> Cpsw_openPortLinkAndPhy start, speed = 2, duplexity = 1
[MCU2_0]      3.463803 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg enetType is 6, macPort 0 ,instId is 0 status is 0
[MCU2_0]      3.463854 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg miiSoc->layerType is 0, miiSoc->sublayerType 2
[MCU2_0]      3.463898 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg mii->layerType is 0, mii->sublayerType 2
[MCU2_0]      3.463975 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (0)
[MCU2_0]      3.464041 s: EnetPhy_open: WLY TEST>>>>>>> EnetPhy_open get hPhy = a233c6c0.
[MCU2_0]      3.464077 s: EnetPhy_open: enetphy.c EnetPhy_open: line 302
[MCU2_0]      3.464104 s: EnetPhy_open: enetphy.c EnetPhy_open: line 319
[MCU2_0]      3.464142 s: EnetPhy_open: enetphy.c EnetPhy_open: line 326
[MCU2_0]      3.464168 s: EnetPhy_open: WLY TEST >>>> alive = 1
[MCU2_0]      3.464197 s: EnetPhy_open: enetphy.c EnetPhy_open: line 344
[MCU2_0]      3.464227 s: EnetPhy_open: enetphy.c EnetPhy_open: line 354
[MCU2_0]      3.464256 s: EnetPhy_bindDriver: enetphy.c EnetPhy_bindDriver: line 1900 
[MCU2_0]      3.464298 s: EnetPhy_bindDriver: 1 PHY 0: OUI:0000c0 Model:00 Ver:03 <-> 'vsc8514'
[MCU2_0]      3.464337 s: EnetPhy_bindDriver: 1 PHY 0: OUI:0000c0 Model:00 Ver:03 <-> 'dp83822'
[MCU2_0]      3.464374 s: EnetPhy_bindDriver: 1 PHY 0: OUI:0000c0 Model:00 Ver:03 <-> 'dp83867'
[MCU2_0]      3.464412 s: EnetPhy_bindDriver: 1 PHY 0: OUI:0000c0 Model:00 Ver:03 <-> 'MARVELL88Q5072'
[MCU2_0]      3.464454 s: EnetPhy_bindDriver: PHY 0: OUI:0000c0 Model:00 Ver:03 <-> 'MARVELL88Q5072' : OK
[MCU2_0]      3.464494 s: EnetPhy_open: enetphy.c EnetPhy_open : line 356, status: 0
[MCU2_0]      3.464531 s: EnetPhy_open: WLY TEST>>>>>>> EnetPhy_open end hPhy = a233c6c0, status = 0.
[MCU2_0]      3.464592 s: EnetBoard_setPhyConfig: WLY TEST >>>> EnetBoard_setPhyConfig start. 6
[MCU2_0]      3.464635 s: EnetBoard_setPhyConfig: V1/enet_appboardutils_j721e_evm.c 845, EnetAppUtils_setNoPhyCfgRgmii portNum 5
[MCU2_0]      3.530719 s: Cpsw_openPortLinkAndPhy: WLY TEST>>>>>>> Cpsw_openPortLinkAndPhy start, speed = 2, duplexity = 1
[MCU2_0]      3.530789 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg enetType is 6, macPort 5 ,instId is 0 status is 0
[MCU2_0]      3.530838 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg miiSoc->layerType is 0, miiSoc->sublayerType 1
[MCU2_0]      3.530883 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg mii->layerType is 0, mii->sublayerType 1
[MCU2_0]      3.530971 s: EnetPhy_open: WLY TEST>>>>>>> EnetPhy_open get hPhy = a233c7d4.
[MCU2_0]      3.531013 s: EnetPhy_open: enetphy.c EnetPhy_open: line 302
[MCU2_0]      3.531042 s: EnetPhy_open: enetphy.c EnetPhy_open: line 319
[MCU2_0]      3.531077 s: EnetPhy_open: enetphy.c EnetPhy_open: line 326
[MCU2_0]      3.531104 s: EnetPhy_open: WLY TEST >>>> alive = 0
[MCU2_0]      3.531139 s: EnetPhy_open: WLY TEST>>>>>>> EnetPhy_open end hPhy = a233c7d4, status = 0.
[MCU2_0]      3.531185 s: CpswMacPort_enablePort: portNum 5, speed 1
[MCU2_0]      3.531215 s: CpswMacPort_enablePort: line 1378 portNum 5, speed 1
[MCU2_0]      3.531258 s: PHY 0 is alive
[MCU2_0]      3.531276 s: PHY 1 is alive
[MCU2_0]      3.531292 s: PHY 2 is alive
[MCU2_0]      3.531308 s: PHY 3 is alive
[MCU2_0]      3.531323 s: PHY 4 is alive
[MCU2_0]      3.531339 s: PHY 5 is alive
[MCU2_0]      3.531355 s: PHY 6 is alive
[MCU2_0]      3.531370 s: PHY 7 is alive
[MCU2_0]      3.531386 s: PHY 8 is alive
[MCU2_0]      3.531402 s: PHY 9 is alive
[MCU2_0]      3.531417 s: PHY 10 is alive
[MCU2_0]      3.531433 s: PHY 11 is alive
[MCU2_0]      3.531461 s: PHY 27 is alive
[MCU2_0]      3.531477 s: PHY 28 is alive
[MCU2_0]      3.531746 s: ETHFW: Version   : 0.01.01
[MCU2_0]      3.531795 s: ETHFW: Build Date: Aug  1, 2022
[MCU2_0]      3.531819 s: ETHFW: Build Time: 13:52:45
[MCU2_0]      3.531839 s: ETHFW: Commit SHA: ddfe210b
[MCU2_0]      3.531864 s: ETHFW: Init ... DONE !!!
[MCU2_0]      3.531887 s: ETHFW: Remove server Init ... !!!
[MCU2_0]      3.533071 s: Remote demo device (core : mcu2_0) .....
[MCU2_0]      3.533126 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]      3.540601 s: Host MAC address: 70:ff:76:1d:92:b2
[MCU2_0]      3.582687 s: FVID2: Init ... !!!
[MCU2_0]      3.582790 s: FVID2: Init ... Done !!!
[MCU2_0]      3.582829 s: VHWA: VPAC Init ... !!!
[MCU2_0]      3.582853 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]      3.583078 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.583106 s: VHWA: LDC Init ... !!!
[MCU2_0]      3.587547 s: VHWA: LDC Init ... Done !!!
[MCU2_0]      3.587594 s: VHWA: MSC Init ... !!!
[MCU2_0]      3.600947 s: VHWA: MSC Init ... Done !!!
[MCU2_0]      3.601001 s: VHWA: NF Init ... !!!
[MCU2_0]      3.603283 s: VHWA: NF Init ... Done !!!
[MCU2_0]      3.603330 s: VHWA: VISS Init ... !!!
[MCU2_0]      3.613051 s: VHWA: VISS Init ... Done !!!
[MCU2_0]      3.613104 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]      3.613143 s:  VX_ZONE_INIT:Enabled
[MCU2_0]      3.613167 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]      3.613187 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]      3.614295 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target IPU1-0 
[MCU2_0]      3.614608 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_NF 
[MCU2_0]      3.614931 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_LDC1 
[MCU2_0]      3.615212 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC1 
[MCU2_0]      3.615493 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC2 
[MCU2_0]      3.615874 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_VISS1 
[MCU2_0]      3.616172 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE1 
[MCU2_0]      3.616464 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE2 
[MCU2_0]      3.616796 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY1 
[MCU2_0]      3.617090 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY2 
[MCU2_0]      3.617361 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CSITX 
[MCU2_0]      3.617666 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE3 
[MCU2_0]      3.617999 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE4 
[MCU2_0]      3.618271 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE5 
[MCU2_0]      3.618545 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE6 
[MCU2_0]      3.618869 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE7 
[MCU2_0]      3.619147 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE8 
[MCU2_0]      3.619195 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[MCU2_0]      3.619223 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]      3.631527 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]      3.631576 s: CSI2RX: Init ... !!!
[MCU2_0]      3.631598 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]      3.631947 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.631981 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]      3.632461 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.632486 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]      3.632691 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.632718 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]      3.632843 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.632867 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]      3.632977 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.633887 s: CSI2RX: Init ... Done !!!
[MCU2_0]      3.633934 s: CSI2TX: Init ... !!!
[MCU2_0]      3.633956 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]      3.634073 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.634099 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]      3.634554 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.634579 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]      3.634917 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.635636 s: CSI2TX: Init ... Done !!!
[MCU2_0]      3.635711 s: UDMA Copy: Init ... !!!
[MCU2_0]      3.638121 s: UDMA Copy: Init ... Done !!!
[MCU2_0]      3.638172 s: IPC: netcheck_ipcInit----wly uds
[MCU2_0]      3.638200 s: ok: register app_netcheck_Init done
[MCU2_0]      3.638223 s: IPC: cameraDebug_ipcInit----
[MCU2_0]      3.638244 s: ok: register app_cameraDebug_Init done
[MCU2_0]      3.638266 s: ISS: Init ... jjjjjjj!!!
[MCU2_0]      3.638305 s: IssSensor_Init 
[MCU2_0]      3.638416 s: setupI2CInst: I2C 0 Open success
[MCU2_0]      3.638506 s: setupI2CInst: I2C 3 Open success
[MCU2_0]      3.638575 s: setupI2CInst: I2C 5 Open success
[MCU2_0]      3.638631 s: register avm_tx
[MCU2_0]      3.638714 s: Found sensor MASTER_AVM at location 0 
[MCU2_0]      3.638760 s: register huayang
[MCU2_0]      3.638806 s: Found sensor MASTER_CAMERA at location 1 
[MCU2_0]      3.638872 s: [IssSensor_PowerOn]pSensorHandle->createPrms->num_channels:0x8
[MCU2_0]      3.638925 s: HuaYang_PowerOn : chMask = 0xf 
[MCU2_0]      3.638962 s: GPIO43:1
[MCU2_0]      3.638990 s: GPIO47:1
[MCU2_0]      3.639015 s: GPIO49:1
[MCU2_0]      3.639039 s: GPIO50:1
[MCU2_0]      3.639062 s: GPIO51:1
[MCU2_0]      3.639081 s: IssSensor_PowerOn failed, status = -1 
[MCU2_0]      3.639264 s: marvell88q5072Phy_reset: PHY 0: reset
[MCU2_0]      3.639310 s: marvell88q5072Phy_reset: PHY 0: reset OK
[MCU2_0]      3.643138 s: 
[MCU2_0] CPSW NIMU application, IP address I/F 1: 192.168.1.203
[MCU2_0]      3.643186 s: EthApp_ipAddrHookFxn: project_id is= 2
[MCU2_0]      3.658810 s: EthFw: TimeSync PTP enabled
[MCU2_0]      3.947354 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]      4.638749 s: [IssSensor_Config_Extend]channel_mask_supported:0xff
[MCU2_0]      4.638802 s: HuaYang_Config:chid=0xf board_id=4009
[MCU2_0]      4.638833 s: wm_dvt_camera_config i2cid 3 chid = 0xf
[MCU2_0]      5.379096 s: Function:CpswProxyServer_registerIpv4MacHandlerCb,HostId:0,Handle:a22a2fbc,CoreKey:38acb7e6, MacAddress:2:57:4d:0:1:70 IPv4Addr:172.16.1.112
[MCU2_0]      5.379346 s: Failed to add Static ARP Entry 
[MCU2_0]      5.379385 s: 
[MCU2_0] ================LLI Table entries=========== 
[MCU2_0]      5.379415 s: 
[MCU2_0] Number of Static ARP Entries: 0 
[MCU2_0]      5.379438 s: 
[MCU2_0] SNo.      IP Address         MAC Address  
[MCU2_0]      5.379460 s: ------    -------------      --------------- 
[MCU2_0]      5.380556 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a22a2fbc,CoreKey:38acb7e6, MacAddress:2:57:4d:0:1:70, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]      5.383590 s: Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:12, Policer Entry:2
[MCU2_0]      5.383640 s: ==hProxyServer->addStaticCfg==
[MCU2_0]      5.383665 s: board_id is= 2
[MCU2_0]      5.386606 s: ===success to add broadcast all ports, state: 0
[MCU2_0]      5.386648 s: ==============Mpu11 multicast add===========
[MCU2_0]      5.389566 s: ===success to add multicast all ports, state: 0
[MCU2_0]      5.389626 s: add_vlanid() add vlanid
[MCU2_0]      5.390204 s: add vlan ioctl OK, port mask:42  vid: 20
[MCU2_0]      5.390251 s: add_vlanid() add vlanid end
[MCU2_0]      6.007965 s: LINK A 0
[MCU2_0]      6.008295 s: LINK B 0
[MCU2_0]      6.008591 s: LINK C 0
[MCU2_0]      6.008882 s: LINK D 0
[MCU2_0]      6.009223 s: readback = 21 i2cid = 3 slave_address= 0x29
[MCU2_0]      6.009259 s: wm_dvt_camera_config read_csi_pll_0 33 status = 0 init_count = 1
[MCU2_0]      6.009293 s: huayang_Config End
[MCU2_0]      6.009321 s: gpioTsk create...
[MCU2_0]      6.009526 s: gpioTsk create successfully
[MCU2_0]      6.009581 s: IssSensor_Init ... Done !!!
[MCU2_0]      6.009724 s: vissRemoteServer_Init ... Done !!!
[MCU2_0]      6.009852 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]      6.009881 s: APP: Init ... Done !!!
[MCU2_0]      6.009902 s: APP: Run ... !!!
[MCU2_0]      6.009919 s: IPC: Starting echo test ...
[MCU2_0]      6.012431 s: APP: Run ... Done !!!
[MCU2_0]      6.014329 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_1[.] C66X_1[.] C66X_2[.] C7X_1[.] 
[MCU2_0]      6.014504 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]      6.014724 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]      6.014857 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]      6.014971 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_0]      6.015107 s: come into uds
[MCU2_1]      2.552126 s: CIO: Init ... Done !!!
[MCU2_1]      2.552512 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_1]      2.552640 s: APP: Init ... !!!
[MCU2_1]      2.552695 s: SCICLIENT: Init ... !!!
[MCU2_1]      2.554569 s: SCICLIENT: DMSC FW version [20.8.7--v2020.08d (Terrific Lla]
[MCU2_1]      2.554785 s: SCICLIENT: DMSC FW revision 0x14  
[MCU2_1]      2.554848 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]      2.554896 s: SCICLIENT: Init ... Done !!!
[MCU2_1]      2.554938 s: UDMA: Init ... !!!
[MCU2_1]      2.561364 s: UDMA: Init ... Done !!!
[MCU2_1]      2.561706 s: MEM: Init ... !!!
[MCU2_1]      2.561745 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!!
[MCU2_1]      2.561800 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
[MCU2_1]      2.561851 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ 94010000 of size 134152192 bytes !!!
[MCU2_1]      2.561894 s: MEM: Init ... Done !!!
[MCU2_1]      2.561913 s: IPC: Init ... !!!
[MCU2_1]      2.561943 s: IPC: 7 CPUs participating in IPC !!!
[MCU2_1]      2.561979 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]      2.562009 s: IPC: HLOS is ready !!!
[MCU2_1]      2.571281 s: IPC: Init ... Done !!!
[MCU2_1]      2.571404 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]      2.572927 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]      2.572982 s: FVID2: Init ... !!!
[MCU2_1]      2.573048 s: FVID2: Init ... Done !!!
[MCU2_1]      2.573073 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]      2.573092 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]      2.573453 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]      2.573480 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]      2.573678 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]      2.573707 s: VHWA: DOF Init ... !!!
[MCU2_1]      2.586191 s: VHWA: DOF Init ... Done !!!

And here is the dump of normal state and abnormal state:

log_dir_ok.tar.gz log_dir_bad.tar.gz

Sikai

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Dear Linda and Tanmay,

1. Do we have any registers to reset the sgmii(serdes) and phy?

Write 0C000110h bit1 to 1 then 0 to trigger reset.

2. We have tried to write 0C000104h bit0 which "Software reset occurs immediately. This bit reads as a zero". However it will keep become 1. So we doubt whether the SGMII is still alive or not.

3. How could we know the status of SGMII?

Read 0C000114h bit0 to see link status.

4. What is the mechanism of link?

5. Could we write any register to force it to link?

6. Need to explain why choose force link instead of auto-negotiation.

7. The only difference is they use GP before and HS now.

8. Try to reset PHY(hardware rst pin) or serdes(05000404/40C). Wait for test results.

Sikai

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Dear Tanmay,

Sorry, the dump uploaded before has no results. Update here:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/2541.logging_5F00_script.shok.tar.gz bad.tar.gz

Sikai

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Here is the original change for SGMII:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1003449/tda4vm-enable-serdes0-lan0-as-sgmii-communication-between-two-tda4vm-fail

0 jian35385 over 3 years ago

TI__Mastermind 23125 points

Notes from 8/10 review by TI team:

1. On failed boards, CPSW_PN_MAC_CONTROL_REG_k register was set to 0x0. This can be either caused by 1). CpswMacPort_configSgmii() called before CpswMacPort_enableSgmiiPort(), for case:

else if (sgmiiMode == ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK),

Note that only for this case SGMII link status register are checked and waited, other cases, the function only enables auto-negotiation.

or, 2). the CPSW_PN_MAC_CONTROL_REG_k register was corrupted after the driver set it.

2. SERDES registers patched:

/* PMA_CMN_REFCLK_INT_MODE */
if(refClk >= CSL_SERDES_REF_CLOCK_100M) /* 100MHz and greater reference clock */
{
CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.SERDES_TOP_CTRL),29,28,0x1);

// add modified 3 line directly change register

CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.SERDES_TOP_CTRL),31,30,0x0);

CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.LANECTRL0),25,24,0x0);

CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.LANALIGN0),5,0,0x0);

look good.

Next debug steps:

1. Tanmay to confirm if case 1) happened for FORCEDLINK case, with ethfw team.

2. Sikai to request UART log of MCU2_0 from a good board to compare.

3. Sikai to work with customer to add UART output at the end of function CpswMacPort_setSgmiiInterface(); this is the function where the PN_MAC_CONTROL registers was set. Since we did not see the error msg in the end of this function "MAC %u: Failed to set SGMII interface: %d\n", we suspect this function was never called in time. please verify.

Jian

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Dear Tanmay and Jian,

Sorry I made a mistake that the ethfw log uploaded before is normal state, here are the comparsion:

Fullscreen 1_R5_ok.txt Download

[MCU2_0]      3.085624 s: CIO: Init ... Done !!!
[MCU2_0]      3.085693 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_0]      3.085733 s: APP: Init ... !!!
[MCU2_0]      3.085750 s: SCICLIENT: Init ... !!!
[MCU2_0]      3.086076 s: SCICLIENT: DMSC FW version [20.8.7--v2020.08d (Terrific Lla]
[MCU2_0]      3.086114 s: SCICLIENT: DMSC FW revision 0x14  
[MCU2_0]      3.086138 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      3.086161 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      3.086181 s: UDMA: Init ... !!!
[MCU2_0]      3.088238 s: UDMA: Init ... Done !!!
[MCU2_0]      3.088291 s: MEM: Init ... !!!
[MCU2_0]      3.088326 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!!
[MCU2_0]      3.088382 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
[MCU2_0]      3.088426 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ 94000000 of size 65536 bytes !!!
[MCU2_0]      3.088470 s: MEM: Init ... Done !!!
[MCU2_0]      3.088489 s: IPC: Init ... !!!
[MCU2_0]      3.088515 s: IPC: 7 CPUs participating in IPC !!!
[MCU2_0]      3.088547 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]      3.088573 s: IPC: HLOS is ready !!!
[MCU2_0]      3.095688 s: IPC: Init ... Done !!!
[MCU2_0]      3.095773 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]      3.096627 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]      3.096679 s: ETHFW: Init ... !!!
[MCU2_0]      3.098375 s: ==get_project_id_for_eth: get_acu_project_id:2 ==
[MCU2_0]      3.098443 s: ETHFW INIT: ==============================================Total ports:2
[MCU2_0]      3.098750 s: CPSW_9G Test on MAIN NAVSS
[MCU2_0]      3.110398 s: EnetBoard_setPhyConfig: WLY TEST >>>> EnetBoard_setPhyConfig start. 6
[MCU2_0]      3.110460 s: EnetBoard_setPhyConfig: V1/enet_appboardutils_j721e_evm.c 833, EnetBoard_setPhyConfigSgmii portNum 0
[MCU2_0]      3.146748 s: Cpsw_openPortLinkAndPhy: WLY TEST>>>>>>> Cpsw_openPortLinkAndPhy start, speed = 2, duplexity = 1
[MCU2_0]      3.146822 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg enetType is 6, macPort 0 ,instId is 0 status is 0
[MCU2_0]      3.146872 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg miiSoc->layerType is 0, miiSoc->sublayerType 2
[MCU2_0]      3.146918 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg mii->layerType is 0, mii->sublayerType 2
[MCU2_0]      3.146993 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (0)
[MCU2_0]      3.147064 s: EnetPhy_open: WLY TEST>>>>>>> EnetPhy_open get hPhy = a2349eb0.
[MCU2_0]      3.147104 s: EnetPhy_open: enetphy.c EnetPhy_open: line 302
[MCU2_0]      3.147133 s: EnetPhy_open: enetphy.c EnetPhy_open: line 319
[MCU2_0]      3.147169 s: EnetPhy_open: enetphy.c EnetPhy_open: line 326
[MCU2_0]      3.147198 s: EnetPhy_open: WLY TEST >>>> alive = 0
[MCU2_0]      3.147231 s: EnetPhy_open: WLY TEST>>>>>>> EnetPhy_open end hPhy = a2349eb0, status = 0.
[MCU2_0]      3.147295 s: EnetBoard_setPhyConfig: WLY TEST >>>> EnetBoard_setPhyConfig start. 6
[MCU2_0]      3.147337 s: EnetBoard_setPhyConfig: V1/enet_appboardutils_j721e_evm.c 845, EnetAppUtils_setNoPhyCfgRgmii portNum 5
[MCU2_0]      3.212736 s: Cpsw_openPortLinkAndPhy: WLY TEST>>>>>>> Cpsw_openPortLinkAndPhy start, speed = 2, duplexity = 1
[MCU2_0]      3.212806 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg enetType is 6, macPort 5 ,instId is 0 status is 0
[MCU2_0]      3.212857 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg miiSoc->layerType is 0, miiSoc->sublayerType 1
[MCU2_0]      3.212901 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg mii->layerType is 0, mii->sublayerType 1
[MCU2_0]      3.212991 s: EnetPhy_open: WLY TEST>>>>>>> EnetPhy_open get hPhy = a2349fc4.
[MCU2_0]      3.213036 s: EnetPhy_open: enetphy.c EnetPhy_open: line 302
[MCU2_0]      3.213066 s: EnetPhy_open: enetphy.c EnetPhy_open: line 319
[MCU2_0]      3.213102 s: EnetPhy_open: enetphy.c EnetPhy_open: line 326
[MCU2_0]      3.213131 s: EnetPhy_open: WLY TEST >>>> alive = 0
[MCU2_0]      3.213163 s: EnetPhy_open: WLY TEST>>>>>>> EnetPhy_open end hPhy = a2349fc4, status = 0.
[MCU2_0]      3.213206 s: CpswMacPort_enablePort: portNum 5, speed 1
[MCU2_0]      3.213243 s: CpswMacPort_enablePort: line 1378 portNum 5, speed 1
[MCU2_0]      3.213527 s: ETHFW: Version   : 0.01.01
[MCU2_0]      3.213577 s: ETHFW: Build Date: Aug 10, 2022
[MCU2_0]      3.213605 s: ETHFW: Build Time: 03:28:40
[MCU2_0]      3.213627 s: ETHFW: Commit SHA: 00541a16
[MCU2_0]      3.213652 s: ETHFW: Init ... DONE !!!
[MCU2_0]      3.213675 s: ETHFW: Remove server Init ... !!!
[MCU2_0]      3.214844 s: Remote demo device (core : mcu2_0) .....
[MCU2_0]      3.214901 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]      3.222430 s: Host MAC address: 70:ff:76:1d:92:b2
[MCU2_0]      3.264706 s: FVID2: Init ... !!!
[MCU2_0]      3.264798 s: FVID2: Init ... Done !!!
[MCU2_0]      3.264837 s: VHWA: VPAC Init ... !!!
[MCU2_0]      3.264858 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]      3.265064 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.265090 s: VHWA: LDC Init ... !!!
[MCU2_0]      3.269380 s: VHWA: LDC Init ... Done !!!
[MCU2_0]      3.269430 s: VHWA: MSC Init ... !!!
[MCU2_0]      3.282634 s: VHWA: MSC Init ... Done !!!
[MCU2_0]      3.282686 s: VHWA: NF Init ... !!!
[MCU2_0]      3.284944 s: VHWA: NF Init ... Done !!!
[MCU2_0]      3.284992 s: VHWA: VISS Init ... !!!
[MCU2_0]      3.296068 s: VHWA: VISS Init ... Done !!!
[MCU2_0]      3.296121 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]      3.296161 s:  VX_ZONE_INIT:Enabled
[MCU2_0]      3.296187 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]      3.296206 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]      3.297279 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target IPU1-0 
[MCU2_0]      3.297552 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_NF 
[MCU2_0]      3.297859 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_LDC1 
[MCU2_0]      3.298139 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC1 
[MCU2_0]      3.298393 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC2 
[MCU2_0]      3.298762 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_VISS1 
[MCU2_0]      3.299062 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE1 
[MCU2_0]      3.299332 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE2 
[MCU2_0]      3.299601 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY1 
[MCU2_0]      3.299940 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY2 
[MCU2_0]      3.300228 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CSITX 
[MCU2_0]      3.300514 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE3 
[MCU2_0]      3.300876 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE4 
[MCU2_0]      3.301195 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE5 
[MCU2_0]      3.301485 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE6 
[MCU2_0]      3.301823 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE7 
[MCU2_0]      3.302131 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE8 
[MCU2_0]      3.302182 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[MCU2_0]      3.302212 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]      3.315426 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]      3.315476 s: CSI2RX: Init ... !!!
[MCU2_0]      3.315497 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]      3.315673 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.315732 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]      3.315908 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.315935 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]      3.316080 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.316104 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]      3.316228 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.316252 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]      3.316364 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.317231 s: CSI2RX: Init ... Done !!!
[MCU2_0]      3.317279 s: CSI2TX: Init ... !!!
[MCU2_0]      3.317301 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]      3.317417 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.317445 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]      3.317853 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.317882 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]      3.318046 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]      3.318752 s: CSI2TX: Init ... Done !!!
[MCU2_0]      3.318793 s: UDMA Copy: Init ... !!!
[MCU2_0]      3.320806 s: UDMA Copy: Init ... Done !!!
[MCU2_0]      3.320856 s: IPC: netcheck_ipcInit----wly uds
[MCU2_0]      3.320885 s: ok: register app_netcheck_Init done
[MCU2_0]      3.320909 s: IPC: cameraDebug_ipcInit----
[MCU2_0]      3.320933 s: ok: register app_cameraDebug_Init done
[MCU2_0]      3.320957 s: ISS: Init ... jjjjjjj!!!
[MCU2_0]      3.320997 s: IssSensor_Init 
[MCU2_0]      3.321097 s: setupI2CInst: I2C 0 Open success
[MCU2_0]      3.321161 s: setupI2CInst: I2C 3 Open success
[MCU2_0]      3.321217 s: setupI2CInst: I2C 5 Open success
[MCU2_0]      3.321263 s: register avm_tx
[MCU2_0]      3.321305 s: Found sensor SLAVER_AVM at location 0 
[MCU2_0]      3.321339 s: register huayang
[MCU2_0]      3.321372 s: Found sensor SLAVER_CAMERA at location 1 
[MCU2_0]      3.321429 s: [IssSensor_PowerOn]pSensorHandle->createPrms->num_channels:0x8
[MCU2_0]      3.321472 s: HuaYang_PowerOn : chMask = 0xff 
[MCU2_0]      3.321503 s: GPIO43:1
[MCU2_0]      3.321526 s: GPIO47:1
[MCU2_0]      3.321549 s: GPIO49:1
[MCU2_0]      3.321570 s: GPIO50:1
[MCU2_0]      3.321591 s: GPIO51:1
[MCU2_0]      3.321611 s: GPIO21:1
[MCU2_0]      3.321632 s: GPIO64:1
[MCU2_0]      3.321652 s: GPIO34:1
[MCU2_0]      3.321673 s: GPIO52:1
[MCU2_0]      3.321732 s: GPIO2:1
[MCU2_0]      3.321757 s: GPIO10:1
[MCU2_0]      3.321781 s: GPIO11:1
[MCU2_0]      3.321804 s: GPIO12:1
[MCU2_0]      3.321826 s: GPIO13:1
[MCU2_0]      3.321842 s: IssSensor_PowerOn failed, status = -1 
[MCU2_0]      3.327246 s: 
[MCU2_0] CPSW NIMU application, IP address I/F 1: 192.168.1.203
[MCU2_0]      3.327295 s: EthApp_ipAddrHookFxn: project_id is= 2
[MCU2_0]      3.342285 s: EthFw: TimeSync PTP enabled
[MCU2_0]      3.599848 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]      4.321762 s: [IssSensor_Config_Extend]channel_mask_supported:0xff
[MCU2_0]      4.321816 s: HuaYang_Config:chid=0xff
[MCU2_0]      4.321845 s: wm_dvt_camera_config i2cid 3 chid = 0xff
[MCU2_0]      4.630859 s: LINK A 0
[MCU2_0]      4.631075 s: LINK B 0
[MCU2_0]      4.631249 s: LINK C 0
[MCU2_0]      4.631412 s: LINK D 0
[MCU2_0]      4.631572 s: LINK A 0
[MCU2_0]      4.631731 s: LINK B 0
[MCU2_0]      4.631901 s: LINK C 0
[MCU2_0]      4.632064 s: LINK D 0
[MCU2_0]      4.632264 s: readback = 61 i2cid = 3 slave_address= 0x6b
[MCU2_0]      4.632460 s: readback = 61 i2cid = 3 slave_address= 0x2d
[MCU2_0]      4.632487 s: wm_dvt_camera_config read_csi_pll_0 0x61 read_csi_pll_1 0x61 status = 0 init_count = 1
[MCU2_0]      4.632530 s: huayang_Config End
[MCU2_0]      4.632555 s: gpioTsk create...
[MCU2_0]      4.632777 s: gpioTsk create successfully
[MCU2_0]      4.632838 s: IssSensor_Init ... Done !!!
[MCU2_0]      4.632934 s: vissRemoteServer_Init ... Done !!!
[MCU2_0]      4.633050 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]      4.633077 s: APP: Init ... Done !!!
[MCU2_0]      4.633098 s: APP: Run ... !!!
[MCU2_0]      4.633114 s: IPC: Starting echo test ...
[MCU2_0]      4.635619 s: APP: Run ... Done !!!
[MCU2_0]      4.637405 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]      4.637567 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]      4.637689 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]      4.637910 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_0]      4.638049 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_0]      5.021631 s: Function:CpswProxyServer_registerIpv4MacHandlerCb,HostId:0,Handle:a22a2fbc,CoreKey:38acb7e6, MacAddress:2:57:4d:0:1:20 IPv4Addr:172.16.1.32
[MCU2_0]      5.021906 s: Failed to add Static ARP Entry 
[MCU2_0]      5.021965 s: 
[MCU2_0] ================LLI Table entries=========== 
[MCU2_0]      5.022000 s: 
[MCU2_0] Number of Static ARP Entries: 0 
[MCU2_0]      5.022024 s: 
[MCU2_0] SNo.      IP Address         MAC Address  
[MCU2_0]      5.022047 s: ------    -------------      --------------- 
[MCU2_0]      5.022792 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a22a2fbc,CoreKey:38acb7e6, MacAddress:2:57:4d:0:1:20, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]      5.025806 s: Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:12, Policer Entry:2
[MCU2_0]      5.025860 s: ==hProxyServer->addStaticCfg==
[MCU2_0]      5.025888 s: board_id is= 2
[MCU2_0]      5.028807 s: ===success to add broadcast all ports, state: 0
[MCU2_0]      5.028848 s: ==============Mpu11 multicast add===========
[MCU2_0]      5.031759 s: ===success to add multicast all ports, state: 0
[MCU2_0]      5.031817 s: add_vlanid() add vlanid
[MCU2_0]      5.032373 s: add vlan ioctl OK, port mask:42  vid: 20
[MCU2_0]      5.032416 s: add_vlanid() add vlanid end
[MCU2_1]      2.254453 s: CIO: Init ... Done !!!
[MCU2_1]      2.254510 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_1]      2.254547 s: APP: Init ... !!!
[MCU2_1]      2.254566 s: SCICLIENT: Init ... !!!
[MCU2_1]      2.254878 s: SCICLIENT: DMSC FW version [20.8.7--v2020.08d (Terrific Lla]
[MCU2_1]      2.254915 s: SCICLIENT: DMSC FW revision 0x14  
[MCU2_1]      2.254938 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]      2.254963 s: SCICLIENT: Init ... Done !!!
[MCU2_1]      2.254983 s: UDMA: Init ... !!!
[MCU2_1]      2.257065 s: UDMA: Init ... Done !!!
[MCU2_1]      2.257137 s: MEM: Init ... !!!
[MCU2_1]      2.257183 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!!
[MCU2_1]      2.257236 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
[MCU2_1]      2.257282 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ 94010000 of size 134152192 bytes !!!
[MCU2_1]      2.257325 s: MEM: Init ... Done !!!
[MCU2_1]      2.257344 s: IPC: Init ... !!!
[MCU2_1]      2.257371 s: IPC: 7 CPUs participating in IPC !!!
[MCU2_1]      2.257404 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]      2.257434 s: IPC: HLOS is ready !!!
[MCU2_1]      2.274496 s: IPC: Init ... Done !!!
[MCU2_1]      2.274838 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]      2.278421 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]      2.278480 s: FVID2: Init ... !!!
[MCU2_1]      2.278571 s: FVID2: Init ... Done !!!
[MCU2_1]      2.278601 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]      2.278622 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]      2.278843 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]      2.278872 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]      2.279017 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]      2.279043 s: VHWA: DOF Init ... !!!
[MCU2_1]      2.289359 s: VHWA: DOF Init ... Done !!!
[MCU2_1]      2.289409 s: VHWA: SDE Init ... !!!
[MCU2_1]      2.293542 s: VHWA: SDE Init ... Done !!!
[MCU2_1]      2.293615 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]      2.293647 s: VHWA: Codec: Init ... !!!
[MCU2_1]      2.293670 s: VHWA: VDEC Init ... !!!
[MCU2_1]      2.308303 s: VHWA: VDEC Init ... Done !!!
[MCU2_1]      2.308356 s: VHWA: VENC Init ... !!!
[MCU2_1]      2.308642 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params
[MCU2_1]      2.349230 s: VHWA: VENC Init ... Done !!!
[MCU2_1]      2.349281 s: VHWA: Init ... Done !!!
[MCU2_1]      2.349317 s:  VX_ZONE_INIT:Enabled
[MCU2_1]      2.349340 s:  VX_ZONE_ERROR:Enabled
[MCU2_1]      2.349360 s:  VX_ZONE_WARNING:Enabled
[MCU2_1]      2.350314 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_SDE 
[MCU2_1]      2.350578 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_DOF 
[MCU2_1]      2.350796 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC1 
[MCU2_1]      2.351027 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC2 
[MCU2_1]      2.351239 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC1 
[MCU2_1]      2.351443 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC2 
[MCU2_1]      2.351490 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[MCU2_1]      2.351548 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]      2.351858 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]      2.351896 s: UDMA Copy: Init ... !!!
[MCU2_1]      2.354021 s: UDMA Copy: Init ... Done !!!
[MCU2_1]      2.354072 s: APP: Init ... Done !!!
[MCU2_1]      2.354097 s: APP: Run ... !!!
[MCU2_1]      2.354115 s: IPC: Starting echo test ...
[MCU2_1]      2.356578 s: APP: Run ... Done !!!
[MCU2_1]      2.357756 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]      2.357977 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[P] 
[MCU2_1]      2.358060 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]      2.358131 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]      4.637225 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[C6x_1 ]      1.998642 s: CIO: Init ... Done !!!
[C6x_1 ]      1.998663 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
[C6x_1 ]      1.998676 s: APP: Init ... !!!
[C6x_1 ]      1.998684 s: SCICLIENT: Init ... !!!
[C6x_1 ]      1.998979 s: SCICLIENT: DMSC FW version [20.8.7--v2020.08d (Terrific Lla]
[C6x_1 ]      1.998992 s: SCICLIENT: DMSC FW revision 0x14  
[C6x_1 ]      1.999001 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]      1.999011 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]      1.999020 s: UDMA: Init ... !!!
[C6x_1 ]      2.001159 s: UDMA: Init ... Done !!!
[C6x_1 ]      2.001180 s: MEM: Init ... !!!
[C6x_1 ]      2.001193 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!!
[C6x_1 ]      2.001210 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]      2.001225 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!!
[C6x_1 ]      2.001241 s: MEM: Init ... Done !!!
[C6x_1 ]      2.001249 s: IPC: Init ... !!!
[C6x_1 ]      2.001264 s: IPC: 7 CPUs participating in IPC !!!
[C6x_1 ]      2.001278 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]      2.001292 s: IPC: HLOS is ready !!!
[C6x_1 ]      2.006062 s: IPC: Init ... Done !!!
[C6x_1 ]      2.006091 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ]      2.006495 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ]      2.006524 s:  VX_ZONE_INIT:Enabled
[C6x_1 ]      2.006534 s:  VX_ZONE_ERROR:Enabled
[C6x_1 ]      2.006543 s:  VX_ZONE_WARNING:Enabled
[C6x_1 ]      2.007136 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[C6x_1 ]      2.007153 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ]      2.007455 s: reg c66x custom ....
[C6x_1 ]      2.007499 s: tivxAddTargetKernelOvxControler : target_name DSP-1 , self_cpu 0 
[C6x_1 ]      2.007586 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ]      2.007600 s: UDMA Copy: Init ... !!!
[C6x_1 ]      2.009520 s: UDMA Copy: Init ... Done !!!
[C6x_1 ]      2.009539 s: APP: Init ... Done !!!
[C6x_1 ]      2.009896 s: APP: Run ... !!!
[C6x_1 ]      2.009910 s: IPC: Starting echo test ...
[C6x_1 ]      2.011194 s: APP: Run ... Done !!!
[C6x_1 ]      2.159157 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_1[P] C66X_1[s] C66X_2[x] C7X_1[x] 
[C6x_1 ]      2.303183 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_1[P] C66X_1[s] C66X_2[x] C7X_1[P] 
[C6x_1 ]      2.303983 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]      2.357618 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]      4.637059 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_2 ]      2.281141 s: CIO: Init ... Done !!!
[C6x_2 ]      2.281165 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
[C6x_2 ]      2.281179 s: APP: Init ... !!!
[C6x_2 ]      2.281187 s: SCICLIENT: Init ... !!!
[C6x_2 ]      2.281806 s: SCICLIENT: DMSC FW version [20.8.7--v2020.08d (Terrific Lla]
[C6x_2 ]      2.281820 s: SCICLIENT: DMSC FW revision 0x14  
[C6x_2 ]      2.281830 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]      2.281840 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]      2.281850 s: UDMA: Init ... !!!
[C6x_2 ]      2.289836 s: UDMA: Init ... Done !!!
[C6x_2 ]      2.289858 s: MEM: Init ... !!!
[C6x_2 ]      2.289871 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!!
[C6x_2 ]      2.289888 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]      2.289903 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!!
[C6x_2 ]      2.289918 s: MEM: Init ... Done !!!
[C6x_2 ]      2.289926 s: IPC: Init ... !!!
[C6x_2 ]      2.289939 s: IPC: 7 CPUs participating in IPC !!!
[C6x_2 ]      2.289952 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]      2.289963 s: IPC: HLOS is ready !!!
[C6x_2 ]      2.297665 s: IPC: Init ... Done !!!
[C6x_2 ]      2.297695 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ]      2.298116 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ]      2.298147 s:  VX_ZONE_INIT:Enabled
[C6x_2 ]      2.298157 s:  VX_ZONE_ERROR:Enabled
[C6x_2 ]      2.298166 s:  VX_ZONE_WARNING:Enabled
[C6x_2 ]      2.298765 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[C6x_2 ]      2.298782 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ]      2.299096 s: reg c66x custom ....
[C6x_2 ]      2.299141 s: tivxAddTargetKernelOvxControler : target_name DSP-2 , self_cpu 1 
[C6x_2 ]      2.299224 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ]      2.299239 s: UDMA Copy: Init ... !!!
[C6x_2 ]      2.301765 s: UDMA Copy: Init ... Done !!!
[C6x_2 ]      2.301784 s: APP: Init ... Done !!!
[C6x_2 ]      2.302231 s: APP: Run ... !!!
[C6x_2 ]      2.302248 s: IPC: Starting echo test ...
[C6x_2 ]      2.303587 s: APP: Run ... Done !!!
[C6x_2 ]      2.304010 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[.] 
[C6x_2 ]      2.304058 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]      2.304212 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]      2.357631 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]      4.637118 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C7x_1 ]      2.295838 s: CIO: Init ... Done !!!
[C7x_1 ]      2.295854 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[C7x_1 ]      2.295868 s: APP: Init ... !!!
[C7x_1 ]      2.295875 s: SCICLIENT: Init ... !!!
[C7x_1 ]      2.296183 s: SCICLIENT: DMSC FW version [20.8.7--v20

Fullscreen R5_error.txt Download

[MCU2_0]      3.048147 s: CIO: Init ... Done !!!
[MCU2_0]      3.048217 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_0]      3.048258 s: APP: Init ... !!!
[MCU2_0]      3.048277 s: SCICLIENT: Init ... !!!
[MCU2_0]      3.048625 s: SCICLIENT: DMSC FW version [20.8.7--v2020.08d (Terrific Lla]
[MCU2_0]      3.048661 s: SCICLIENT: DMSC FW revision 0x14
[MCU2_0]      3.048682 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      3.048705 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      3.048725 s: UDMA: Init ... !!!
[MCU2_0]      3.050535 s: UDMA: Init ... Done !!!
[MCU2_0]      3.050590 s: MEM: Init ... !!!
[MCU2_0]      3.050623 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!!
[MCU2_0]      3.050677 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
[MCU2_0]      3.050724 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ 94000000 of size 65536 bytes !!!
[MCU2_0]      3.050768 s: MEM: Init ... Done !!!
[MCU2_0]      3.050786 s: IPC: Init ... !!!
[MCU2_0]      3.050813 s: IPC: 7 CPUs participating in IPC !!!
[MCU2_0]      3.050847 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]      3.050876 s: IPC: HLOS is ready !!!
[MCU2_0]      3.057889 s: IPC: Init ... Done !!!
[MCU2_0]      3.057943 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]      3.058811 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]      3.058869 s: ETHFW: Init ... !!!
[MCU2_0]      3.060279 s: ==get_project_id_for_eth: get_acu_project_id:2 ==
[MCU2_0]      3.060339 s: ETHFW INIT: ==============================================Total ports:2
[MCU2_0]      3.060630 s: CPSW_9G Test on MAIN NAVSS
[MCU2_0]      3.072526 s: EnetBoard_setPhyConfig: WLY TEST >>>> EnetBoard_setPhyConfig start. 6
[MCU2_0]      3.072591 s: EnetBoard_setPhyConfig: V1/enet_appboardutils_j721e_evm.c 833, EnetBoard_setPhyConfigSgmii portNum 0
[MCU2_0]      3.108273 s: Cpsw_openPortLinkAndPhy: WLY TEST>>>>>>> Cpsw_openPortLinkAndPhy start, speed = 2, duplexity = 1
[MCU2_0]      3.108348 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg enetType is 6, macPort 0 ,instId is 0 status is 0
[MCU2_0]      3.108397 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg miiSoc->layerType is 0, miiSoc->sublayerType 2
[MCU2_0]      3.108443 s: CpswMacPort_checkSocCfg: CpswMacPort_checkSocCfg mii->layerType is 0, mii->sublayerType 2
[MCU2_0]      3.108518 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (0)
[MCU2_0]      3.108561 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (1)
[MCU2_0]      3.108600 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (2)
[MCU2_0]      3.108638 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (3)
[MCU2_0]      3.108675 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (4)
[MCU2_0]      3.108713 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (5)
[MCU2_0]      3.108750 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (6)
[MCU2_0]      3.108788 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (7)
[MCU2_0]      3.108825 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (8)
[MCU2_0]      3.108862 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (9)
[MCU2_0]      3.108900 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (10)
[MCU2_0]      3.108937 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (11)
[MCU2_0]      3.108975 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (12)
[MCU2_0]      3.109013 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (13)
[MCU2_0]      3.109050 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (14)
[MCU2_0]      3.109088 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (15)
[MCU2_0]      3.109126 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (16)
[MCU2_0]      3.109163 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (17)
[MCU2_0]      3.109201 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (18)
[MCU2_0]      3.109261 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (19)
[MCU2_0]      3.109302 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (20)
[MCU2_0]      3.109341 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (21)
[MCU2_0]      3.109378 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (22)
[MCU2_0]      3.109416 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (23)
[MCU2_0]      3.109454 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (24)
[MCU2_0]      3.109491 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (25)
[MCU2_0]      3.109529 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (26)
[MCU2_0]      3.109567 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (27)
[MCU2_0]      3.109605 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (28)
[MCU2_0]      3.109642 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (29)
[MCU2_0]      3.109680 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (30)
[MCU2_0]      3.109718 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (31)
[MCU2_0]      3.109755 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (32)
[MCU2_0]      3.109793 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (33)
[MCU2_0]      3.109831 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (34)
[MCU2_0]      3.109869 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (35)
[MCU2_0]      3.109906 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (36)
[MCU2_0]      3.109944 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (37)
[MCU2_0]      3.109982 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (38)
[MCU2_0]      3.110019 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (39)
[MCU2_0]      3.110057 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (40)
[MCU2_0]      3.110095 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (41)
[MCU2_0]      3.110132 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (42)
[MCU2_0]      3.110170 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (43)
[MCU2_0]      3.110207 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (44)
[MCU2_0]      3.110255 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (45)
[MCU2_0]      3.110295 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (46)
[MCU2_0]      3.110333 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (47)
[MCU2_0]      3.110371 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (48)
[MCU2_0]      3.110409 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (49)
[MCU2_0]      3.110446 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (50)
[MCU2_0]      3.110484 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (51)
[MCU2_0]      3.110522 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (52)
[MCU2_0]      3.110559 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (53)
[MCU2_0]      3.110597 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (54)
[MCU2_0]      3.110635 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (55)
[MCU2_0]      3.110673 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (56)
[MCU2_0]      3.110710 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (57)
[MCU2_0]      3.110748 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (58)
[MCU2_0]      3.110785 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (59)
[MCU2_0]      3.110823 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (60)
[MCU2_0]      3.110861 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (61)
[MCU2_0]      3.110899 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (62)
[MCU2_0]      3.110937 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (63)
[MCU2_0]      3.110974 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (64)
[MCU2_0]      3.111012 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (65)
[MCU2_0]      3.111050 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (66)
[MCU2_0]      3.111088 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (67)
[MCU2_0]      3.111126 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (68)
[MCU2_0]      3.111163 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (69)
[MCU2_0]      3.111201 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (70)
[MCU2_0]      3.111245 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (71)
[MCU2_0]      3.111284 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (72)
[MCU2_0]      3.111322 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (73)
[MCU2_0]      3.111360 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (74)
[MCU2_0]      3.111397 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (75)
[MCU2_0]      3.111435 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (76)
[MCU2_0]      3.111473 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (77)
[MCU2_0]      3.111511 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (78)
[MCU2_0]      3.111549 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (79)
[MCU2_0]      3.111586 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (80)
[MCU2_0]      3.111624 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (81)
[MCU2_0]      3.111662 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (82)
[MCU2_0]      3.111700 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (83)
[MCU2_0]      3.111737 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (84)
[MCU2_0]      3.111775 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (85)
[MCU2_0]      3.111813 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (86)
[MCU2_0]      3.111851 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (87)
[MCU2_0]      3.111888 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (88)
[MCU2_0]      3.111926 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (89)
[MCU2_0]      3.111964 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (90)
[MCU2_0]      3.112001 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (91)
[MCU2_0]      3.112039 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (92)
[MCU2_0]      3.112077 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (93)
[MCU2_0]      3.112114 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (94)
[MCU2_0]      3.112152 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (95)
[MCU2_0]      3.112190 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (96)
[MCU2_0]      3.112233 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (97)
[MCU2_0]      3.112272 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (98)
[MCU2_0]      3.112311 s: CpswMacPort_configSgmii: Wait for SGMII link>>>>>>>>>>>>>>>>>>>>>>>>>>> (99)

Sikai

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Dear Experts,

1. If we have requirement of the boot sequence between TDA4 and Switch?

2. Replace bad chip with good chip in factory and test.

3. Is it normal that we do not need to configure MAC before configuring SGMII to achieve Link status?

4. Who decide the link status?

Sikai

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Dear Experts,

The phenomenon is:

1. We use CCS to stop at the entry of CpswMacPort_configSgmii()

From the code logic we can see at this moment we have not config MAC:

And when we stop at the entry we have not configure SGMII:

2. When in abnormal state:

a) 0C000114 = 00000030

b) 0C000120 = 00000000

c) 0C022330 = 00040000

3. When work in abnormal state:

a) 0C000114 = 00000031

b) 0C000120 = 00004001

c) 0C022330 = 000400A0

Here are some questions:

1. Is this initialization step right?(Config Sgmii then MAC and do CpswMacPort_configSgmii() earlier than CpswMacPort_enableSgmiiPort() )

2. TDA4 will be powered on first then Switch. Will this have any effect?

3. Who will set Link Partner status?

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

4.Who will set this two bits once we have set EXT_EN, software or hardware? If it is handled by hardware why it will show different values sometimes?

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Dear Experts,

We tried to reset serdes in Board_CfgSgmii( ) from EnetBoard_setPhyConfigSgmii( ).

We use CCS to debug step by step and find the register will change when we complete CSL_serdesLaneEnable( ):

1. 0x0C000114 will change, within 5 times it can change to 0x00000031

2. 0x05000488 will change. When in abnoraml state, 0x05000488 will be all 0.

So we step into CSL_serdesLaneEnable( ) to see when we set the 0x05000488 register:

It shows in CSL_serdesReleaseReset

So here is our question:

1. Why in normal board reset PHY once is enough while in abnormal board it has possibility that link status will not be updated?

2. Any ideas to further locate the problem?

Sikai

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

0 Linda Wang over 3 years ago

Prodigy 110 points

Hi, Tanmay and Sikai,

We got a bad board register dump and a good board register dump are down below, please help us to check it.

Thanks

0 Linda Wang over 3 years ago

Prodigy 110 points

Hi, engineers of TI,

As you talked in meeting, we try to this:

1.disable PCIE in linux

2.programed just use LANE0, and don't used LANE1 We can see the register value, the PCIE is disable:

This is where we change in the serdes code,

but still, we get 0x38 in link status register: 0x0c000114, but we get a correct value in register 0x050004cc.

So it seems like it did't work if we disable PCIE

Regards,

Linda Wang

0 Sikai Lu over 3 years ago

TI__Expert 3241 points

Here are the eye graph from both end of link of RX.

We also dump the related registers when power on:

Fullscreen 上电 dump reg.log Download

MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000400 = 0x69856002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000404 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000408 = 0x0A000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500040C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000410 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000414 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000418 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500041C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000420 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000424 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000428 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500042C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000430 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000434 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000438 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500043C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000440 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000444 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000448 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500044C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000450 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000454 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000458 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500045C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000460 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000464 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000468 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500046C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000470 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000474 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000478 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500047C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000480 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000484 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000488 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500048C = 0x00000002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000490 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000494 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000498 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500049C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004AC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004BC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004CC = 0x00000002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004DC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004EC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004FC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000500 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000504 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000508 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500050C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000510 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000514 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000518 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500051C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000520 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000524 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000528 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500052C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000530 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000534 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000538 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500053C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000540 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000544 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000548 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500054C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000550 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000554 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000558 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500055C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000560 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000564 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000568 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500056C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000570 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000574 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000578 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500057C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000580 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000584 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000588 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500058C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000590 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000594 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000598 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500059C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005AC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005BC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005CC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005DC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005EC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F4 = 0x001D0000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005FC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F000 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F004 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F008 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F00C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F010 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F014 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F018 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F01C = 0x00000000

Before reset:

Fullscreen before Serdes Reset.log Download

MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000400 = 0x69856002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000404 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000408 = 0x1A000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500040C = 0x31000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000410 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000414 = 0x80000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000418 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500041C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000420 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000424 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000428 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500042C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000430 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000434 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000438 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500043C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000440 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000444 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000448 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500044C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000450 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000454 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000458 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500045C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000460 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000464 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000468 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500046C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000470 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000474 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000478 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500047C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000480 = 0x70800000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000484 = 0x00010002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000488 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500048C = 0x00000002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000490 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000494 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000498 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500049C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004AC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004BC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C0 = 0x70800000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C4 = 0x00010002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004CC = 0x00000002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004DC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004EC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004FC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000500 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000504 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000508 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500050C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000510 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000514 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000518 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500051C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000520 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000524 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000528 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500052C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000530 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000534 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000538 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500053C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000540 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000544 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000548 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500054C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000550 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000554 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000558 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500055C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000560 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000564 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000568 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500056C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000570 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000574 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000578 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500057C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000580 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000584 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000588 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500058C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000590 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000594 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000598 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500059C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005AC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005BC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005CC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005DC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005EC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F4 = 0x001D0000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005FC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F000 = 0x00009010
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F004 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F008 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F00C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F010 = 0x00002D0F
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F014 = 0x00001000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F018 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F01C = 0x00000000

When in link down:

Fullscreen after Serdes reset link down.log Download

MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000400 = 0x69856002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000404 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000408 = 0x1A000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500040C = 0xB1000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000410 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000414 = 0x80000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000418 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500041C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000420 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000424 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000428 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500042C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000430 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000434 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000438 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500043C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000440 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000444 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000448 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500044C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000450 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000454 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000458 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500045C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000460 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000464 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000468 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500046C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000470 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000474 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000478 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500047C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000480 = 0x70800000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000484 = 0x00010002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000488 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500048C = 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000490 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000494 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000498 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500049C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004AC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004BC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C0 = 0x70800000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C4 = 0x00010002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004CC = 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004DC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004EC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004FC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000500 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000504 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000508 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500050C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000510 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000514 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000518 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500051C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000520 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000524 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000528 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500052C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000530 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000534 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000538 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500053C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000540 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000544 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000548 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500054C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000550 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000554 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000558 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500055C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000560 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000564 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000568 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500056C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000570 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000574 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000578 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500057C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000580 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000584 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000588 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500058C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000590 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000594 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000598 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500059C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005AC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005BC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005CC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005DC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005EC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F4 = 0x001C0000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005FC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F000 = 0x0000B030
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F004 = 0x00080000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F008 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F00C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F010 = 0x00002D0F
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F014 = 0x01001000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F018 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F01C = 0x00000000

And when in link up:

Fullscreen after Serdes reset link up.log Download

MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000400 = 0x69856002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000404 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000408 = 0x1A000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500040C = 0xB1000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000410 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000414 = 0x80000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000418 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500041C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000420 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000424 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000428 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500042C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000430 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000434 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000438 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500043C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000440 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000444 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000448 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500044C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000450 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000454 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000458 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500045C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000460 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000464 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000468 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500046C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000470 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000474 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000478 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500047C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000480 = 0x70800000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000484 = 0x00010002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000488 = 0x00000001
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500048C = 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000490 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000494 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000498 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500049C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004A8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004AC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004B8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004BC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C0 = 0x70800000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C4 = 0x00010002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004C8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004CC = 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004D8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004DC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004E8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004EC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004F8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050004FC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000500 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000504 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000508 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500050C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000510 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000514 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000518 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500051C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000520 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000524 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000528 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500052C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000530 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000534 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000538 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500053C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000540 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000544 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000548 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500054C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000550 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000554 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000558 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500055C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000560 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000564 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000568 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500056C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000570 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000574 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000578 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500057C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000580 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000584 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000588 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500058C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000590 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000594 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x05000598 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500059C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005A8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005AC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005B8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005BC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005C8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005CC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005D8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005DC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E4 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005E8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005EC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F4 = 0x001C0000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005F8 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x050005FC = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F000 = 0x0000B030
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F004 = 0x00080000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F008 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F00C = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F010 = 0x00002D0F
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F014 = 0x01001000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F018 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x0500F01C = 0x000AF944

Sikai

0 Sikai Lu over 3 years ago in reply to Sikai Lu

TI__Expert 3241 points

Dear Experts,

After we set a default configuration of the RST pin of Marvell's switch. We have run the pressure test on several boards and it works fine.

However here are several new questions happened during the process:

1. We need to set the GPIO AH21 low when powering on and set it high after APP starts up. So we add this logic in SBL, however when we try to pull the GPIO down in MCU2_0, it fails. They also tried to pull it down in A72, it can work. Linda will post their change here.

2. During the process they also found the PHY_RESET function did not run during the initialization.

3. During the process they find one board will have high possiblity to reproduce the similiar issue of this link:https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1080303/tda4vm-cpsw9g-mdio-not-alive

Sikai

0 Sikai Lu over 3 years ago in reply to Sikai Lu

TI__Expert 3241 points

Dear Experts,

After pressure tests, the error still reproduces in 1178 times. Here are some ponits hope to get an explanation:

1. When we pull down GPIO in SBL and pull up after system boot up, it takes over 1000 times to reproduce. However, if we pull down and pull up GPIO both in the very beginning of MCU2_0, it only takes dozens of times to reproduce.

So why the time sequence will have such huge influence?

2. They are using MAC-MAC to connect serdes and switch. From my point of view, once power on with correct configuration then the link status should be up right? So in this case, it has possibilty that the link status will not update, is it caused by mis-configuration of serdes?

Sikai

0 Sikai Lu over 2 years ago in reply to Sikai Lu

TI__Expert 3241 points

Dear Experts,

Thanks for Field team's onsite support, we have successfully combine the two workaround together. And after 3000+ times tests, only 1/3650 possibility to boot within 50ms which is the longest time.

Customer will verify it in real cars later.

Sikai

Processors

Processors forum

TDA4VM: TDA4 isn't update sgmii link status in the initialization phase