Hi TI,
I have got two questions regarding MCSPI module in TDA4VM:
The TRM (SPRUIL1C) states in Table 12-60 about the MCSPI Master Clock Rates, that 50MHz and 25MHz "are not necessarily supported by all MCSPI modules. For more information, see the Timing Requirements". The mentioned Timing Requirements are located in the Datasheet, but unfortunately, I could not find any helpful information about this topic. Therefore, I looked up the corresponding PLL frequencies for MCSPI modules in Main and in MCU Domain. I found out that
- MCU Domain is sourced by MCU_PLL2_HSDIV0_CLKOUT
- Main Domain is sourced by MAIN_PLL0_HSDIV5_CLKOUT
Looking up the correct frequencies via TISCI User Guide (https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/pll_data.html), I found out that all MCSPI instances in TDA4VM are sourced with 50MHz.
Q1 :Since I also did not find any exceptions in the corresponding MCSPI Registers, my conclusion is, that all MCSPI modules in TDA4VM support up to 50 MHz. Can you please confirm this?
That datasheet (SPRSP36J) states in a note in chapter 7.10.5.18, that "The IO timings provided in this section are applicable for all combinations of signals for MCU_SPI0 and MCU_SPI1. However, the timings are only valid for MCU_SPI0 and MCU_SPI1 if signals within a single IOSET are used. The IOSETs are defined in the Table 7-75 and Table 7-76 tables".
Since this note is eclusively referring to MCSPI modules in MCU domain, I am a little bit concerned about MCSPI modules in main domain.
Q2: Is there any difference for timing requirements for MCSPI modules in Main Domain?
Thanks for your help and best regards,
Felix
