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TDA4VM: PCIE issue

Part Number: TDA4VM

Hi team,

Here're few questions from the customer may need your help:

1) Can the PCIe clock be generated internally? Or must an external clock generator be required?

If so, can the clock be output to an external PCIe device on the PCIe_REFCLK pin? 

2) Below is a rough diagram of the TDA4 PCIe connection, could you help check is it OK? 

3) TDA4 Serdes0 pairs to Switch, TDA4 uses QSGMII, Switch uses 5GBASE-R. Are the two protocols compatible? 

4) Could you help give a EMMC list supported by TDA4VM?

5) Is the clock source internal to pcie0/pcie1/pcie2 the same?

6) MAIN RGMII must be 1.8 V for 1000M operation? Does the 3.3V level support 1000M? 

Could you help check this case? Thanks.

Best Regards,

Cherry

  • Hi,

    May I know is there any update on this?

    Thanks and regards,

    Cherry

  • Cherry, 

    sorry for the delay. please see notes under your questions:

    1) Can the PCIe clock be generated internally? Or must an external clock generator be required?

    If so, can the clock be output to an external PCIe device on the PCIe_REFCLK pin? 

    [Jian] PCIe refclks can be sourced from internal PLLs in TDA4. Additionally, PCIe_REFCLK1/2/3_P/M can be used to output refclk to clock devices connected to the PCIe ports. note that some software patch is needed to enable the output buffers.  

    2) Below is a rough diagram of the TDA4 PCIe connection, could you help check is it OK? 

    [Jian] I checked SERDES muxing scheme, all PCIe looks good. Ethernet may have an issue - QSGMII is not compatible with 5GBASE-R, thought they both support 5Gbps. To interface with the switch, you will need USXGMII running at 5Gbps, but that is not enabled by software in TDA4 presently. 

    3) TDA4 Serdes0 pairs to Switch, TDA4 uses QSGMII, Switch uses 5GBASE-R. Are the two protocols compatible? 

    [Jian] already answered above. 

    4) Could you help give a EMMC list supported by TDA4VM? 

    [Jian] will let Shiou Mei to answer. 

    5) Is the clock source internal to pcie0/pcie1/pcie2 the same?

    [Jian] yes. they are from the same PLL path. But you should still use individual REFCLKn-P/M pins instead of externally splitting a single source, due to 1). jitter issues; 2). reset and clock enabling sequence are tied to each PCIe ports. 

    6) MAIN RGMII must be 1.8 V for 1000M operation? Does the 3.3V level support 1000M?

    [Jian] I recall saw something in the datasheet on RGMII switching characteristics. but will let Shreyas to comment. 

  • Cherry,

    We don't have a list to share with customer as TDA4VM should support all eMMC compatible with JEDEC eMMC v5.1 specification.  If you need a part number for reference, we use MTFC16GAPALBH on our EVM.

  • Hi Jian and Shiou Mei,

    Thanks for your support! Have forwarded your response to the end customer.

    Thanks and regards,

    Cherry