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TMS320C6748: Precharge command before self-refresh command for mDDR

Tony Tang
Mastermind 28922 points
Part Number: TMS320C6748

From mDDR spec, there should be a Precharge command before self-refresh command, We captured signal, did not find Precharge command, only enter self-refresh command.

DDR2 spec doesn't need precharge command before entering self-refresh command. The DDR control behave same for DDR2 and mDDR.

Enter self refresh as below form gel:

hotmenu enter_ddr_selfrefresh()
{
//*(unsigned int *)0xc0000000 =0xaaaa5555;

EMIFDDR_SDRCR &= ~(1<<23);
EMIFDDR_SDRCR |=1<<31;

}

As with Winbond mDDR has problem on exit self refresh, and it need precharge command as below

Is there any special command to send out precharge command with enter self refresh command?

  • 0
    TI__Guru* 85960 points

    Tony, I'm not sure why this isn't happening for mDDR.  Can you ensure all timing in SDTIMR1 and SDTIMR2 are correct especially tRP, tXP, tXSNR, tXSRD, tRTP.  Also ensure PASR=0.   

     A precharge is issued before all refresh commands.  Does the Winbond device consider the prechange from a previous refresh command?  Maybe the controller doesn't issue a precharge before the self-refresh because a precharge was already issued with the previous refresh command.

    Regards,

    James

  • 0 in reply to JJD
    TI__Mastermind 28922 points

    James,

    There is no precharge command before refresh command also.

    I was using gel file initialized ddr controller:

    DDR2:  C:\ti\ccsv6\ccs_base\emulation\boards\lcdkc6748\gel\C6748.gel

    mDDR: C:\ti\ccsv6\ccs_base\emulation\boards\evmc6748\gel\C6748.gel

  • 0 in reply to Tony Tang
    TI__Guru* 85960 points

    I'm not sure why you would see this behavior.  If it is behaving like a DDR2, maybe something is wrong with the initialization sequence, and the controller is actually initialized as a DDR2 inadvertently.  Are all of the init steps properly executed?  Maybe try a second init sequence?  Are you seeing functional errors with the memory?

    Regards,

    James