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AM5716: Boot from HS200 eMMC

Tony Tang
Mastermind 29962 points

Part Number: AM5716

From TRM, Initial SDR- and DDR- modes supported

Can a HS200 supported eMMC be used as booting device? and switch to HS200 mode in Kernel after booting?

  • 0
    TI__Guru**** 167880 points

    Hi Tony,

    Please take a look at this commit:

    commit e74adafb04b908a5f007994138e46237a49e9bfd
    Author: Jean-Jacques Hiblot <jjhiblot@ti.com>
    Date:   Tue Jan 30 16:01:51 2018 +0100

        dts: am57xx-idk: disable HS200 support
        
        HS200 cannot be supported on mmc2, because the IO lines of mmc2 are
        connected to 3.3v.
        
        Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>

    diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi
    index 97aa8e6a56..fa5a078b27 100644
    --- a/arch/arm/dts/am57xx-idk-common.dtsi
    +++ b/arch/arm/dts/am57xx-idk-common.dtsi
    @@ -413,6 +413,8 @@
            bus-width = <8>;
            ti,non-removable;
            max-frequency = <96000000>;
    +       no-1-8-v;
    +       /delete-property/ mmc-hs200-1_8v;
     };

    So mmc2 is the eMMC instance. It is not supported on am57xx.

    - Keerthy

  • 0 in reply to Keerthy J
    TI__Mastermind 29962 points

    Keerthy,

    Thanks, So that is the case of AM57xx IDK hardware limitation? from device level, it can support HS200?

  • 0 in reply to Tony Tang
    TI__Prodigy 405 points

    Tony,  Yes, according to the device datamanual, MMC2 supports HS200 from the device level.

  • 0 in reply to Keerthy J
    TI__Mastermind 29962 points

    Keerthy,

    If remove the no-1.8-v from the MMC node, it will support HS200 eMMC? and what is the frequency of HS200? can it output 200MHz/192MHz eMMC clock?

    &mmc2 {
    status = "okay";
    vmmc-supply = <&v3_3d>;
    vqmmc-supply = <&v3_3d>;
    bus-width = <8>;
    non-removable;
    /*max-frequency = <96000000>; */
    /* no-1-8-v; */
    };

    From the boot log, should add pinmux for hs200 to enable hs200 mode?

    [ 2.263475] sdhci-omap 480b4000.mmc: Linked as a consumer to regulator.3
    [ 2.270275] sdhci-omap 480b4000.mmc: Dropping the link to regulator.3
    [ 2.276828] sdhci-omap 480b4000.mmc: Linked as a consumer to regulator.3
    [ 2.283696] sdhci-omap 480b4000.mmc: no pinctrl state for ddr_1_8v mode
    [ 2.290343] sdhci-omap 480b4000.mmc: no pinctrl state for hs200_1_8v mode
    [ 2.323011] mmc1: SDHCI controller on 480b4000.mmc [480b4000.mmc] using ADMA

    how to apply the mmc2_pins_hs200 dra72x-mmc-iodelay.dtsi to am571x-idk.dtsi mmc2 node to enable HS200?

    mmc2_pins_hs200: mmc2_pins_hs200 {
    pinctrl-single,pins = <
    DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    >;

    //am57xx-idk-common.dtsi

    &mmc2 {
    status = "okay";
    vmmc-supply = <&v3_3d>;
    vqmmc-supply = <&v3_3d>;
    bus-width = <8>;
    non-removable;
    /* max-frequency = <96000000>; */
    /* no-1-8-v; */
    };

    // am571x-idk.dtsi

    &mmc2 {
    pinctrl-names = "default", "hs", "ddr_3_3v";
    pinctrl-0 = <&mmc2_pins_default>;
    pinctrl-1 = <&mmc2_pins_hs>;
    pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
    };

    According to this post: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/658498/linux-am5728-mmc-device-tree-bindings/

    in dra7.dtsi file, the compatible should change to compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";?

    mmc2: mmc@480b4000 {
    compatible = "ti,dra7-sdhci";  // change to  "ti,dra7-hsmmc", "ti,omap4-hsmmc";
    reg = <0x480b4000 0x400>;
    interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "mmc2";
    status = "disabled";
    max-frequency = <192000000>;
    /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
    sdhci-caps-mask = <0x7 0x0>;
    mmc-hs200-1_8v;
    mmc-ddr-1_8v;
    mmc-ddr-3_3v;
    };