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OMAP-L138: Additional Read Operation.

Matsukawa Tadahiro
Prodigy 40 points
Part Number: OMAP-L138
Other Parts Discussed in Thread: ADS8557,

Following is stated on Page 876 of SPRUH77C–April 2013–Revised September 2016

"The EMIFA may be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIFA immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay"

What is required for additional read operations ?

When I tried to read 6 datas(16 bits) from A/D converter TI ADS8557, OMAP-L138 had six separated read operations.

- Bus width of EMAIF is 16 bits. Read address is the same at each reads, because continuous acsess is required at AD8557 six read operations  

Best, Regards

 

  • 0
    TI__Guru* 88080 points

    I don't think anything is required, the controller will handle the read accesses.  I think the scenario it is talking about is if, for example, a processor issues a 32-bit access, but the bus is only 16-bits.  The controller has to break this up into two read accesses.  There would be no turnaround cycle delay in this case.

    You probably are issuing 16-bit read from the A/D, so that is why you would get an equal number of reads.

    Regards,

    james

  • 0 in reply to JJD
    Prodigy 40 points

    Dear, JJD

    Thank you for your addvice.

    I tried to read 32-bit data.

    But the controller has only one read operation, not two. - It seems one 16bit read operation.

    Note: Bus accsess was monitered by FPGA implemented on the same board.

    I set ASIZE=1 (Data Bus With = 16bit) in CEnCFG register.

    Is another settenig required?

     Best, Reguards

  • 0 in reply to Matsukawa Tadahiro
    TI__Guru* 88080 points

    I don't think anything else is required.  You may want to use SS=1 so you see the individual strobes for each 16-bit access.

    Regards,

    James