TDA4VM-Q1: TDA4VH&TDA4VM-Q1 PCIE PHY

Haitang, 

I understand your want to use the TDA4VH in a similar way as a standard PCIe switch. I believe you can enumerate the PCIe space where RC and see the EPe via TDA4VH, but the probing should happen in the following order:

EP2 go into link training ready

TDA4VH's EP ports ready, in parallel that TDA4VH/s RC port probes EP2

X86 PC probes TDA4VH

This is different than our standard demo of:

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/08_02_00_03/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_Backplane.html

so I will check with our team to see if there are potential issues mapping the address space between a EP port and an RC port. 

will update once I receive response. 

jian

Hi,jian

Thanks for reply the issue.

---------TDA4VH's EP ports ready, in parallel that TDA4VH/s RC port probes EP2

Q1: when  the TDA4VH/TDA4VM  start with PCIE link traning ? 

Q2: the  TDA4VM/TDA4VH PCIE0 setup as RC ，Can we have the patch  to support the MSI interrupt souce code ？

Q3:the PCIE setup as RC ,can PCIE has a PF/VF device to use UDMA-P to send data to by other EP to the soc DDR : 

       data-path likes :  TDA4VM  DDR ------EP BAR -------SOC DDR 

Q4:Can we have a PCIE programming guide ?