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TDA4VM: Timeout during frequency handshake

sun ruijie
Intellectual 603 points
Part Number: TDA4VM

Hi TI teams,

     we modify LPDDR4 frequency from 4266MTS to 3733MTS，

refer to the link：TDA4VM： how to reduce DDR speed to 3733 MTS - Processors forum - Processors - TI E2E support forums，

but found the board print the error log：

Thanks

  • 0
    TI__Guru**** 475655 points

    Hi Sun Ruijie,

    The image is not visible, can you please share it again?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 603 points

    U-Boot SPL 2021.01-g02bf8f1c2b (Jul 18 2022 - 08:17:20 +0000)
    Model: Texas Instruments K3 J721E SoC
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.9.1--v2021.09a (Terrific Lla')
    Timeout during frequency handshake

    ### ERROR ### Please RESET the board ###
    resetting ...

  • 0 in reply to sun ruijie
    TI__Guru**** 162430 points

    Hi Sun,

    Which SDK are you on? Did the reverts work correctly? Can you share the steps you did on your setup?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 603 points

    Hi keerthy，

    on 8.2 SDK， the steps is：

    cd $PSDKLA_PATH/board-support/u-boot-2021.01+gitAUTOINC+53e79d0e89-g53e79d0e89
    git revert 2f21e5b897755334d9a4f2aaacd6945dd2f99cd4
    git revert de779d94c7f2b66f0506f44bfc78c2a3e000ecc5
    git revert 88f9f21f7ad78a80d1375ee2e7b71ac3ab261b6c
    make uboot

    Thanks，

    Ruijie Sun

     

  • 0 in reply to sun ruijie
    TI__Guru**** 162430 points

    Hi,

    Followed the exact same steps on 8.2 SDK.

    k3conf dump clock 47
    |--------------------------------------------------------------------------------|
    | VERSION INFO |
    |--------------------------------------------------------------------------------|
    | K3CONF | (version v0.1-45-g79f007c built Wed Mar 23 21:04:31 UTC 2022) |
    | SoC | J721E SR2.0 |
    | SYSFW | ABI: 3.1 (firmware version 0x0016 '22.1.1--v2022.01 (Terrific Llam)') |
    |--------------------------------------------------------------------------------|

    |---------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name | Status | Clock Frequency |
    |---------------------------------------------------------------------------------------|
    | 47 | 0 | DEV_DDR0_DDRSS_VBUS_CLK | CLK_STATE_READY | 1000000000 |
    | 47 | 1 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
    | 47 | 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 933000000 |
    | 47 | 3 | DEV_DDR0_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 |
    | 47 | 4 | DEV_DDR0_DDRSS_IO_CK_N | CLK_STATE_READY | 0 |
    | 47 | 5 | DEV_DDR0_DDRSS_IO_CK | CLK_STATE_READY | 0 |
    |---------------------------------------------------------------------------------------|

    DDR clk is 933000000  * 4 = 3733 MTS.

    Hope you copied all the binaries to SD card. Please try the above command.


    Best Regards,
    Keerthy

  • 0 in reply to Keerthy J
    Intellectual 603 points

    hi keerthy，

    yes，it is right

    root@optimus:/# k3conf dump clock 47
    |--------------------------------------------------------------------------------|
    | VERSION INFO |
    |--------------------------------------------------------------------------------|
    | K3CONF | (version 0.2-nogit built Tue May 31 07:06:22 UTC 2022) |
    | SoC | J721E SR2.0 |
    | SYSFW | ABI: 3.1 (firmware version 0x0015 '21.9.1--v2021.09a (Terrific Lla)') |
    |--------------------------------------------------------------------------------|

    |---------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name | Status | Clock Frequency |
    |---------------------------------------------------------------------------------------|
    | 47 | 0 | DEV_DDR0_DDRSS_VBUS_CLK | CLK_STATE_READY | 1000000000 |
    | 47 | 1 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
    | 47 | 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 933000000 |
    | 47 | 3 | DEV_DDR0_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 |
    | 47 | 4 | DEV_DDR0_DDRSS_IO_CK_N | CLK_STATE_READY | 0 |
    | 47 | 5 | DEV_DDR0_DDRSS_IO_CK | CLK_STATE_READY | 0 |
    |---------------------------------------------------------------------------------------|

    Thanks，

    Ruijie Sun