Other Parts Discussed in Thread: TDA4VM
Hi,
Please help provide the internal pin dealy data of TDA4VM-Q1 for the same length of LPDDR4 layout traces.
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Below is the on-package pin delay for each of the LPDDR4 signals (for TDA4VM)
Net | Delay (ps) |
DDR0_ATB0 | 25.60 |
DDR0_ATB1 | 36.12 |
DDR0_CA0 | 40.47 |
DDR0_CA1 | 40.29 |
DDR0_CA2 | 40.53 |
DDR0_CA3 | 42.49 |
DDR0_CA4 | 39.76 |
DDR0_CA5 | 41.63 |
DDR0_CAL0 | 42.71 |
DDR0_CKE0 | 43.19 |
DDR0_CKE1 | 39.94 |
DDR0_CKN | 42.68 |
DDR0_CKP | 43.66 |
DDR0_CSN0_0 | 45.43 |
DDR0_CSN0_1 | 39.29 |
DDR0_CSN1_0 | 47.99 |
DDR0_CSN1_1 | 40.56 |
DDR0_DM0 | 61.84 |
DDR0_DM1 | 51.93 |
DDR0_DM2 | 34.79 |
DDR0_DM3 | 31.10 |
DDR0_DQ0 | 62.93 |
DDR0_DQ1 | 62.45 |
DDR0_DQ2 | 61.75 |
DDR0_DQ3 | 62.30 |
DDR0_DQ4 | 61.86 |
DDR0_DQ5 | 62.56 |
DDR0_DQ6 | 63.94 |
DDR0_DQ7 | 63.32 |
DDR0_DQ8 | 52.97 |
DDR0_DQ9 | 52.55 |
DDR0_DQ10 | 52.84 |
DDR0_DQ11 | 52.90 |
DDR0_DQ12 | 50.25 |
DDR0_DQ13 | 51.93 |
DDR0_DQ14 | 50.69 |
DDR0_DQ15 | 50.39 |
DDR0_DQ16 | 32.50 |
DDR0_DQ17 | 32.72 |
DDR0_DQ18 | 32.28 |
DDR0_DQ19 | 31.99 |
DDR0_DQ20 | 34.83 |
DDR0_DQ21 | 32.23 |
DDR0_DQ22 | 34.58 |
DDR0_DQ23 | 32.83 |
DDR0_DQ24 | 31.63 |
DDR0_DQ25 | 31.21 |
DDR0_DQ26 | 33.99 |
DDR0_DQ27 | 31.74 |
DDR0_DQ28 | 30.70 |
DDR0_DQ29 | 30.73 |
DDR0_DQ30 | 31.07 |
DDR0_DQ31 | 31.33 |
DDR0_DQS0N | 62.59 |
DDR0_DQS0P | 61.50 |
DDR0_DQS1N | 50.94 |
DDR0_DQS1P | 51.44 |
DDR0_DQS2N | 33.35 |
DDR0_DQS2P | 34.17 |
DDR0_DQS3N | 33.33 |
DDR0_DQS3P | 32.35 |
DDR0_RESETN | 42.82 |
DDR_RET | 39.68 |
Hi,
In addition to LPDDR4, please help provide the pin delay of other pins, such as SGMII,thanks!
We do not have this level of data for any other pins, as the delay is small compared to the overall signal rate.
The previously provided LPDDR4 pin delay data unit is ps. The customer converts it according to 1ps=5mil. It is found that the LPDDR4 isometric simulation has a huge difference. It is suspected that the conversion relationship is incorrect.
Can you provide the following pin delay data in units of mil, or provide the conversion relationship between ps and mil in the TDA4.
Pin delay cannot be provided in length (mils), as the delay is more than just trace length. It may include other constructions like vias. All Jacinto LPDDR4 requirements are also provided in time (ps).
That conversion is PCB stack-up (material) dependent, which is why TI provides the measurement in time. For my estimations, I use 170ps per inch for standard FR4 material. But that is an estimation only.