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SK-TDA4VM: few questions regarding reference design

Cherry Zhou
Mastermind 22235 points
Part Number: SK-TDA4VM

Hi team,

Here're few questions from the customer may need your help:

https://e2echina.ti.com/cfs-file/__key/communityserver-discussions-components-files/120/5102.PROC112E2_2800_001_29005F00_SCH.pdf

In the above reference design, three SWB1A, SWB2A, SWB3A outputs are combined to one output VDD_CPU_AVS:

1) On P44, it requires FB_B1 and FB_B2 to use a class differential routing, why? 

2) On P44, FB_B2 directly connected to DGND, why? 

3) On P44, U17 chip FB_B3 is connected to vsys_IO_3V3 which is the output voltage of U27.

Is it for voltage monitoring of vsys_IO_3V3? How does detailed monitoring work and how to turn on this monitoring feature? Is there any documents for reference? 

4) On P45, vsys_IO_3V3 connected to FB_B4 of U8 chip and also used for voltage monitoring vsys_IO_3V3.

Is it redundant to repeat the voltage monitoring of vsys_IO_3V3? Or are there any special considerations? 

5) The input voltage and output voltage are monitored by the PMIC chip TPS65941. What happens to the PMIC or what is the next action when Vout/Vin exceeds the threshold value? 

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Mastermind 22235 points

    Hi,

    May I know is there any update?

    Thanks and regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Mastermind 45070 points

    I think some of you questions are answered in the power solution user guide: https://www.ti.com/lit/pdf/slvuc99

    Q1: When operating in dual or triple phase, that is the way the PMIC device is designed (sense differentially)

    Q2:  Again, dual/triple phase PMIC is setup to sense differentially between VDD and GND.

    Q3:  B3 can optionally be used to sense other voltage.  For this design, its setup to sense the IO 3v3 supply.  (This is optional)

    Q4:  The redundancy is not required.

  • 0
    TI__Guru 54826 points

    Hello,

    Cherry Zhou said:

    4) On P45, vsys_IO_3V3 connected to FB_B4 of U8 chip and also used for voltage monitoring vsys_IO_3V3.

    Is it redundant to repeat the voltage monitoring of vsys_IO_3V3? Or are there any special considerations? 

    I am not familiar with the naming convention you are using, so I will attempt to respond in the context of the PMIC document already referenced,  https://www.ti.com/lit/pdf/slvuc99 .

    The secondary PMIC has two voltage feedback monitors available which are not part of the power on sequence. In section 7.4 there is a description on how the processor can configure these feedback pins at runtime.  By default these monitors are not used.  This is different from the feedback pin FB_B3 on the primary pmic which is part of the default power sequence.  If this feedback is not required (functional safety requirements are met some other way) then you can simply connect the FB_B3 to VCCA.  FB-B3 cannot be left unused because during the power up sequence the PMIC is expecting the 3.3V to be present and will treat the absence as a fault.

    Cherry Zhou said:
    The input voltage and output voltage are monitored by the PMIC chip TPS65941. What happens to the PMIC or what is the next action when Vout/Vin exceeds the threshold value?

    This will depend upon which output regulator the fault occurs on.  There are two rail groups in this PDN, MCU and SOC(MAIN).  If there is a failure in the MCU rail group, then this will result in an MCU_POWER_ERR and trigger a shutdown of all PMIC regulators and an automatic recovery attempt. Please see  section 6.2 PFSM Triggers and Figure 6.1. If the failure is on an SOC domain rail then the PMIC will transition to the PWR SOC Error state which only leaves on the regulators associated with the MCU safety Island.  From here the safety island can attempt to clear the interrupt and perform a power up of the SOC(MAIN) rails.   Group definitions can be found in table 5-7.

    In the case of an MCU power error the PMIC will only re-attempt the power sequence 15 times if the failure remains.  After 15 times a power cycle of the system is required.  The number of retries of the SOC power error is left to the decision of the processor.

    Regards,
    Chris