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AM5726: MCSPI Transmission with TX FiFO, possible?

Rasty Slutsker
Expert 1450 points
Part Number: AM5726

Hi,

We need to create uninterrupted transmission over SPI channel.

We enabled TX FIFO and make sure that we fill FIFO and do not get "FIFO full" condition.

Logic analyzer shows random gaps in clock between 16-bit frames (SPI is configured as 16-bit).

Does TI implementation guaranty that gapless SPI  transmission under condition that TX FIFO does not get empty?

Thanks

Rasty

  • 0
    TI__Guru**** 399120 points

    Hi Rasty,

    Are you using DMA for transferring data? If not, can you please try with DMA enabled? 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 1450 points

    Hi

    Some background: 

    We do not use DMA transfer, just polling. In the past we had problems with DMA , long discussion with TI support, finally gave up and used polling instead.

    We feed data to TX register in tight loop (we actually use original TI polling driver with slight modification, where we check that FIFO is not full instead waiting till buffer gets empty). 

    3 questions

    1. Will DMA transfer do what I need?

    2. What happens if I need to send more data with DMA than TX FIFO can handle? Can I chain DMA transfers without using interrupts?

    3. We feed data into FIFO in ight loop at high priority and keep it (TX FIFO) not empty. Why do I see gaps? What is the explanation for gaps?

    Best regards

    Rasty

  • 0 in reply to Rasty Slutsker
    TI__Guru** 113800 points

    Rasty,

    Can you please confirm the SDK version that is being used ?

    Regards

    Karthik

  • 0 in reply to Karthik Ramanan
    Expert 1450 points

    Hi,

    We use pdk_am57xx_1_0_10

    I compared it with pdk_am57xx_1_0_19.

    Nothing significantly changed in this area.

    Best regards

    Rasty

  • 0 in reply to Rasty Slutsker
    TI__Guru**** 399120 points

    Hi Rasty,

    Please find below answers to your questions.

    Rasty Slutsker said:
    We do not use DMA transfer, just polling. In the past we had problems with DMA , long discussion with TI support, finally gave up and used polling instead.

    When you use polling mechanism, how do you ensure that this code is not getting preempted by some other task on the same core? or by some other interrupt routine? Are you using any other task on this core? Also is the code running out of DDR or some internal memory? Because all of these conditions can potentially delay submission to the SPI and then there could be gaps between SPI transfer. 

    What is the packer size that you are using?

    Rasty Slutsker said:
    1. Will DMA transfer do what I need?

    Well, there is a possibility to use DMA for this purpose.

    Rasty Slutsker said:
    2. What happens if I need to send more data with DMA than TX FIFO can handle? Can I chain DMA transfers without using interrupts?

    Yes, DMA channels can be chained to keep the FIFO full.

    Rasty Slutsker said:
    3. We feed data into FIFO in ight loop at high priority and keep it (TX FIFO) not empty. Why do I see gaps? What is the explanation for gaps?

    Please check above questions.

    Regards,

    Brijesh