we are using the DSI PLL Configuration to generate the pixel clock for dpi output by enabling the following two configuration
DSI support
Use DSI PLL for PCLK
After enabling the above configuration we are able to generate higher and more precise pixel clocks for dvi output, otherwise it was not possible to generate the precise pixel clocks for higher resolution such as 1024x768 and 1280x720. But the problem with this configuration is that when we enable multiple display support through overlay manager such that
overlay0 -> DVI.
overlay1 -> DVI.
overlay2 -> TV.
it gives the following error saying it cannot generate required pixel clock for both output together.
omapdss DISPC error: failed to set up scaling, required fclk rate = 737278500 Hz, current fclk rate = 432000000 Hz
omapdss MANAGER error: dispc_setup_plane failed for ovl 2 omapdss MANAGER error: configure_overlay 2 failed
But if i remove the DSI configuration i am able to have multiple display support through overlay but i ma not able to get the precise pixel clocks.
Regards
Imtiyaj