OMAP-L138 Local reset is not done

Hi Frank, can you try the example here?

Your problem might be that the ARM is not in supervisor mode. There are instructions in the wiki above which could fix that issue.

Jeff

By the way, for silicon revision 2.0 and higher the KICK registers are no longer necessary, so you can remove those lines from your code.

Jeff

Hello Jeff,

that the ARM is not in supervisor mode is not the problem (see below), do you have any further ideas, suggestions?

I downloaded newest OMAPL138-DSP-LED-v4.zip from your link and flashed (SPI1) via the below cfg file (just by using the delivered *out files without any modification).
I'm also adding the debug output for the ARM and DSP.

After booting from SPI1 flash LEDs are blinking.
When I now connect the emulator to the ARM9, Register CPSR is 0x800000D3, this means Supervisor mode.
The Module Status Register of the DSP is indicating 0x00001D03 (ARM status is indicating 0x00001F03), same as in my original post.
This means according SPRUGM7D on page 137 of 273: LRSTDONE for the DSP is 0: Local reset is not done.
Could it be, that it is somehow related to the ROM Status Code: 0x00000001 (Description:C674X_0: GEL Output: DSP was put to sleep)?

Thanks,
Frank

===============================   CFG   =======================

Boot Mode=SPI1 Flash
Boot Speed=1
Flash Width=0
Flash Timing=3ffffffc
Configure Peripheral=True
Configure PLL0=False
Configure SDRAM=False
Configure PLL1=False
Configure DDR2=False
Configure LPSC=True
Configure Pinmux=False
Enable CRC=False
Specify Entrypoint=False
Enable Sequential Read=False
Use 4.5 Clock Divider=False
Use DDR2 Direct Clock=False
Use mDDR=True
ROM ID=2
Device Type=0
Input Clock Speed=24
Clock Type=0
PLL0 Pre Divider=2
PLL0 Multiplier=25
PLL0 Post Divider=1
PLL0 Div1=1
PLL0 Div3=3
PLL0 Div7=6
PLL1 Multiplier=20
PLL1 Post Divider=2
PLL1 Div1=1
PLL1 Div2=2
PLL1 Div3=3
Entrypoint=0
SDRAM SDBCR=0
SDRAM SDTMR=0
SDRAM SDRSRPDEXIT=0
SDRAM SDRCR=0
DDR2 PHY=0
DDR2 SDCR=0
DDR2 SDCR2=0
DDR2 SDTIMR=0
DDR2 SDTIMR2=0
DDR2 SDRCR=0
LPSC0 Enable=15+
LPSC0 Disable=
LPSC0 SyncRst=
LPSC1 Enable=
LPSC1 Disable=
LPSC1 SyncRst=
Pinmux=4:2200+
App File String=C:\boot_examples_v4\OMAPL138-DSP-LED\ARM\Debug\OMAPL138-DSP-LED-ARM.out;C:\boot_examples_v4\OMAPL138-DSP-LED\DSP\Debug\OMAPL138-DSP-LED-DSP.out
AIS File Name=C:\boot_examples_v4\OMAPL138-DSP-LED\OMAPL138-DSP-LED-NAND-SPI-UART.h

===============================   ARM   =======================

ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: |             Device Information            |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000
ARM9_0: GEL Output: DEV_INFO_02 = 0x0000000C
ARM9_0: GEL Output: DEV_INFO_03 = 0x00000032
ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000
ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0
ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5523007-12-52-26
ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,15161
ARM9_0: GEL Output: -----
ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003
ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000
ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output:
ARM9_0: GEL Output: -----
ARM9_0: GEL Output: DEV_INFO_20 = 0x30303864
ARM9_0: GEL Output: DEV_INFO_21 = 0x3630306B
ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864
ARM9_0: GEL Output: DEV_INFO_23 = 0x3630306B
ARM9_0: GEL Output: -----
ARM9_0: GEL Output: DEV_INFO_24 = 0x0C01A034
ARM9_0: GEL Output: DEV_INFO_25 = 0x0054463F
ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
ARM9_0: GEL Output: DEV_INFO_26 = 0x76720002
ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: |               BOOTROM Info                |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: ROM ID: d800k006
ARM9_0: GEL Output: Silicon Revision 2.0
ARM9_0: GEL Output: Boot Mode: SPI1 Flash
ARM9_0: GEL Output:
ROM Status Code: 0x00000000
Description:ARM9_0: GEL Output: No error
ARM9_0: GEL Output:
Program Counter (PC) = 0x80018A24
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: |              Clock Information             |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: PLLs configured to utilize crystal.
ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
ARM9_0: GEL Output:
ARM9_0: GEL Output: NOTE:  All clock frequencies in following PLL sections are based
ARM9_0: GEL Output: off OSCIN = 24 MHz.  If that value does not match your hardware
ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,
ARM9_0: GEL Output: and then reload.
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: |              PLL0 Information             |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: PLL0_PREDIV = 24 MHz
ARM9_0: GEL Output: PLL0_PLLOUT = 480 MHz
ARM9_0: GEL Output: PLL0_PLLOUT_POSTDIV = 240 MHz
ARM9_0: GEL Output: PLL0_PLLEN = 24 MHz
ARM9_0: GEL Output: PLL0_SYSCLK1 = 24 MHz
ARM9_0: GEL Output: PLL0_SYSCLK2 = 12 MHz
ARM9_0: GEL Output: PLL0_SYSCLK3 = 24 MHz
ARM9_0: GEL Output: PLL0_SYSCLK4 = 6 MHz
ARM9_0: GEL Output: PLL0_SYSCLK5 = 24 MHz
ARM9_0: GEL Output: PLL0_SYSCLK6 = 24 MHz
ARM9_0: GEL Output: PLL0_SYSCLK7 = 4 MHz
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: |              PLL1 Information             |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: PLL1_PLLOUT = 480 MHz
ARM9_0: GEL Output: PLL1_PLLOUT_POSTDIV = 240 MHz
ARM9_0: GEL Output: PLL1_PLLEN = 24 MHz
ARM9_0: GEL Output: PLL1_SYSCLK1 = 24 MHz
ARM9_0: GEL Output: PLL1_SYSCLK2 = 12 MHz
ARM9_0: GEL Output: PLL1_SYSCLK3 = 24 MHz
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: |              PSC0 Information             |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: State Decoder:
ARM9_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
ARM9_0: GEL Output:  1 = SyncReset (reset assered, clock on)
ARM9_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
ARM9_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
ARM9_0: GEL Output: >3 = Transition in progress
ARM9_0: GEL Output:
ARM9_0: GEL Output: Module 0: EDMA3CC (0)        STATE = 0
ARM9_0: GEL Output: Module 1: EDMA3 TC0          STATE = 0
ARM9_0: GEL Output: Module 2: EDMA3 TC1          STATE = 0
ARM9_0: GEL Output: Module 3: EMIFA (BR7)        STATE = 0
ARM9_0: GEL Output: Module 4: SPI 0              STATE = 0
ARM9_0: GEL Output: Module 5: MMC/SD 0           STATE = 0
ARM9_0: GEL Output: Module 6: AINTC              STATE = 3
ARM9_0: GEL Output: Module 7: ARM RAM/ROM        STATE = 3
ARM9_0: GEL Output: Module 9: UART 0             STATE = 0
ARM9_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8)  STATE = 3
ARM9_0: GEL Output: Module 11: SCR 1 (BR4)        STATE = 3
ARM9_0: GEL Output: Module 12: SCR 2 (BR3/5/6)    STATE = 3
ARM9_0: GEL Output: Module 13: PRUSS              STATE = 0
ARM9_0: GEL Output: Module 14: ARM                STATE = 3
ARM9_0: GEL Output: Module 15: DSP                STATE = 3
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: |              PSC1 Information             |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: State Decoder:
ARM9_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
ARM9_0: GEL Output:  1 = SyncReset (reset assered, clock on)
ARM9_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
ARM9_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
ARM9_0: GEL Output: >3 = Transition in progress
ARM9_0: GEL Output:
ARM9_0: GEL Output: Module 0: EDMA3CC (1)        STATE = 0
ARM9_0: GEL Output: Module 1: USB0 (2.0)         STATE = 0
ARM9_0: GEL Output: Module 2: USB1 (1.1)         STATE = 0
ARM9_0: GEL Output: Module 3: GPIO               STATE = 0
ARM9_0: GEL Output: Module 4: UHPI               STATE = 0
ARM9_0: GEL Output: Module 5: EMAC               STATE = 0
ARM9_0: GEL Output: Module 6: DDR2 and SCR F3    STATE = 0
ARM9_0: GEL Output: Module 7: MCASP0 + FIFO      STATE = 0
ARM9_0: GEL Output: Module 8: SATA               STATE = 0
ARM9_0: GEL Output: Module 9: VPIF               STATE = 0
ARM9_0: GEL Output: Module 10: SPI 1              STATE = 3
ARM9_0: GEL Output: Module 11: I2C 1              STATE = 0
ARM9_0: GEL Output: Module 12: UART 1             STATE = 0
ARM9_0: GEL Output: Module 13: UART 2             STATE = 0
ARM9_0: GEL Output: Module 14: MCBSP0 + FIFO      STATE = 0
ARM9_0: GEL Output: Module 15: MCBSP1 + FIFO      STATE = 0
ARM9_0: GEL Output: Module 16: LCDC               STATE = 0
ARM9_0: GEL Output: Module 17: eHRPWM (all)       STATE = 0
ARM9_0: GEL Output: Module 18: MMC/SD 1           STATE = 0
ARM9_0: GEL Output: Module 19: UPP                STATE = 0
ARM9_0: GEL Output: Module 20: eCAP (all)         STATE = 0
ARM9_0: GEL Output: Module 21: EDMA3 TC2          STATE = 0
ARM9_0: GEL Output: Module 24: SCR-F0 Br-F0       STATE = 3
ARM9_0: GEL Output: Module 25: SCR-F1 Br-F1       STATE = 3
ARM9_0: GEL Output: Module 26: SCR-F2 Br-F2       STATE = 3
ARM9_0: GEL Output: Module 27: SCR-F6 Br-F3       STATE = 3
ARM9_0: GEL Output: Module 28: SCR-F7 Br-F4       STATE = 3
ARM9_0: GEL Output: Module 29: SCR-F8 Br-F5       STATE = 3
ARM9_0: GEL Output: Module 30: Br-F7 (DDR Contr)  STATE = 3
ARM9_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3

===============================   DSP   =======================

C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |             Device Information            |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x0000000C
C674X_0: GEL Output: DEV_INFO_03 = 0x00000032
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5523007-12-52-26
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,15161
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3630306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x0C01A034
C674X_0: GEL Output: DEV_INFO_25 = 0x0054463F
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_26 = 0x76720002
C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |               BOOTROM Info                |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k006
C674X_0: GEL Output: Silicon Revision 2.0
C674X_0: GEL Output: Boot Mode: SPI1 Flash
C674X_0: GEL Output:
ROM Status Code: 0x00000001
Description:C674X_0: GEL Output: DSP was put to sleep
C674X_0: GEL Output:
Program Counter (PC) = 0x80010964
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              Clock Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLLs configured to utilize crystal.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output:
C674X_0: GEL Output: NOTE:  All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 24 MHz.  If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL0_PREDIV = 24 MHz
C674X_0: GEL Output: PLL0_PLLOUT = 480 MHz
C674X_0: GEL Output: PLL0_PLLOUT_POSTDIV = 240 MHz
C674X_0: GEL Output: PLL0_PLLEN = 24 MHz
C674X_0: GEL Output: PLL0_SYSCLK1 = 24 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 12 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 24 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 6 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 24 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 24 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 4 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL1_PLLOUT = 480 MHz
C674X_0: GEL Output: PLL1_PLLOUT_POSTDIV = 240 MHz
C674X_0: GEL Output: PLL1_PLLEN = 24 MHz
C674X_0: GEL Output: PLL1_SYSCLK1 = 24 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 12 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 24 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0: EDMA3CC (0)        STATE = 0
C674X_0: GEL Output: Module 1: EDMA3 TC0          STATE = 0
C674X_0: GEL Output: Module 2: EDMA3 TC1          STATE = 0
C674X_0: GEL Output: Module 3: EMIFA (BR7)        STATE = 0
C674X_0: GEL Output: Module 4: SPI 0              STATE = 0
C674X_0: GEL Output: Module 5: MMC/SD 0           STATE = 0
C674X_0: GEL Output: Module 6: AINTC              STATE = 3
C674X_0: GEL Output: Module 7: ARM RAM/ROM        STATE = 3
C674X_0: GEL Output: Module 9: UART 0             STATE = 0
C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8)  STATE = 3
C674X_0: GEL Output: Module 11: SCR 1 (BR4)        STATE = 3
C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6)    STATE = 3
C674X_0: GEL Output: Module 13: PRUSS              STATE = 0
C674X_0: GEL Output: Module 14: ARM                STATE = 3
C674X_0: GEL Output: Module 15: DSP                STATE = 3
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0: EDMA3CC (1)        STATE = 0
C674X_0: GEL Output: Module 1: USB0 (2.0)         STATE = 0
C674X_0: GEL Output: Module 2: USB1 (1.1)         STATE = 0
C674X_0: GEL Output: Module 3: GPIO               STATE = 0
C674X_0: GEL Output: Module 4: UHPI               STATE = 0
C674X_0: GEL Output: Module 5: EMAC               STATE = 0
C674X_0: GEL Output: Module 6: DDR2 and SCR F3    STATE = 0
C674X_0: GEL Output: Module 7: MCASP0 + FIFO      STATE = 0
C674X_0: GEL Output: Module 8: SATA               STATE = 0
C674X_0: GEL Output: Module 9: VPIF               STATE = 0
C674X_0: GEL Output: Module 10: SPI 1              STATE = 3
C674X_0: GEL Output: Module 11: I2C 1              STATE = 0
C674X_0: GEL Output: Module 12: UART 1             STATE = 0
C674X_0: GEL Output: Module 13: UART 2             STATE = 0
C674X_0: GEL Output: Module 14: MCBSP0 + FIFO      STATE = 0
C674X_0: GEL Output: Module 15: MCBSP1 + FIFO      STATE = 0
C674X_0: GEL Output: Module 16: LCDC               STATE = 0
C674X_0: GEL Output: Module 17: eHRPWM (all)       STATE = 0
C674X_0: GEL Output: Module 18: MMC/SD 1           STATE = 0
C674X_0: GEL Output: Module 19: UPP                STATE = 0
C674X_0: GEL Output: Module 20: eCAP (all)         STATE = 0
C674X_0: GEL Output: Module 21: EDMA3 TC2          STATE = 0
C674X_0: GEL Output: Module 24: SCR-F0 Br-F0       STATE = 3
C674X_0: GEL Output: Module 25: SCR-F1 Br-F1       STATE = 3
C674X_0: GEL Output: Module 26: SCR-F2 Br-F2       STATE = 3
C674X_0: GEL Output: Module 27: SCR-F6 Br-F3       STATE = 3
C674X_0: GEL Output: Module 28: SCR-F7 Br-F4       STATE = 3
C674X_0: GEL Output: Module 29: SCR-F8 Br-F5       STATE = 3
C674X_0: GEL Output: Module 30: Br-F7 (DDR Contr)  STATE = 3
C674X_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3

Hello Jeff,

is the statement, that "for silicon revision 1.1 and higher the KICK registers are no longer necesarry" also valid for clearing CHIPINTn Interrupts?

In which data sheet / user's guide for the OMAP-L138 is it described, that the Kick registers are no longer necessary for revisions 1.1 and 2.0?

Thanks,

Frank

It is actually just silicon revision 2.0 and later that removed the need to use the KICK registers. The details are in section 3.1.2 of the silicon errata.

Jeff

So to clarify, you are able to run the DSP blink example successfully? If so that means that the DSP is out of reset and running the code. You should also not see any ROM error messages if the LEDs are blinking.

Jeff

Hello Jeff,

I had a look in section 3.1.2 of the errata for OMAP-L137 (SPRZ291E) and OMAP-L138 (SPRZ301E).

The following sentence is only in the errata for the OMAP-L137:

"Starting with silicon revision 2.0, the KICK registers will be disabled and the SYSCFG registers will be permanently accessible. Writes to the disabled KICK registers will have no effect."

Is the statement also valid for OMAP-L138 and just missing in ther errata?
Or is the boot loader unlocking SYSCFG registers via the KICK registers and the behavior is the same as for revisions 1.1 and 1.0?

Thanks,
Frank

Hello Jeff,

yes, the example from OMAPL138-DSP-LED-v4.zip is running, LEDS are toggling.

Do you have an experimenter kit (or an eval board) to run the example out of flash?

So currently two open questions:

Q1: Why do I have the ROM error message "DSP was put to sleep"?
Q2: Why is Module Status Register of the DSP is indicating 0x00001D03 (Local reset is not done)?

Some more information, might help you:

- When I load my own project (as described in my first post) and let the DSP run in the shared ram (0x80000000), the ROM error message is the same as for the DSP blink example ("DSP was put to sleep").

- When I Assert local reset (set LRST bit of PSC0 MDCTL-15 to 0) the Module Status Register of the DSP is indicating 0x00001E03.
- When I De-assert local reset (set LRST bit of PSC0 MDCTL-15 to 1) the Module Status Register of the DSP is indicating 0x00001D03.
Assertion/De-assertion was done within the emulator.

Thanks,
Frank

Looks like it is missing from the errata. I know that for 2.0 they have been disabled but I'm looking into whether they were still enabled in 1.1.

Jeff

Q1) For OMAP-L138, the DSP comes up first, enables the ARM, and then goes to sleep. So the last message reported by the DSP bootloader was that it went to sleep. Once your program wakes up the DSP again, that ROM status register does not get updated anymore, which is why you still see that message.

Q2) The LRSTDONE bit is an indication that the DSP cache invalidation cycles have completed after assertion (low) of LRST.. This does not need to be checked when de-asserting LRST.

Jeff

Hello Jeff,

so the BOOTROM Info must be seen just as a status and not as an error for the DSP and the "DSP was put to sleep" is therfore OK, correct?

LRSTDONE bit:
- You're saying "This does not need to be checked when de-asserting LRST".
- SPRUGM7D is stating "Local reset done. Software is responsible for checking if local reset is done before accessing this module. This bit applies to ARM module (module 14) and DSP module (module 15). This field is 1 for all other modules."

In my original post I was asking if there is something missing/wrong, as "LRSTDONE for the DSP is 0: Local reset is not done." when DSP and ARM images are running.
What is the reason that the DSP module is indicating "Local reset is not done"?
That the ARM is not in supervisor mode is already excluded by running the images from OMAPL138-DSP-LED-v4.zip (see ealier posts in this thread).
Do you have an eval board / experimenter kit that you can run the examples from the zip files out of SPI1 flash and have a look at the LRSTDONE bit?
Could it be that documentation for the DSP in SPRUGM7D is wrong?

Kick register:
If it is not possible for the OMAP-L138 revision 2.0 to lock the SYSCFG module,
it would be great if this would be not only added to the errata, but also to SPRUGM7D (section 11.2.2 Kicker Mechanism Protection).

Thanks,
Frank

Yes the "DSP was put to sleep" is correct and not an error. That is the last stage of the DSP bootloader.

For the LRSTDONE, that indicates that the process of putting the device in reset has completed. When coming out of reset, this bit is not relevant and should not be checked. As you have seen, this bit will be cleared when the module is out of reset and set after the module is put in reset and teh cache invalidation cycles have been complete. We can update the documentation to make this clearer.

For the KICK registers, this indeed should be in the errata, and it will appear in the next revision. Thanks,

Jeff