DRA821U: about GPIO_VIRT

tomitama

Part Number: DRA821U

I am checking "9.4 Interrupt Sources" in TRM (Rev. A).
I think GPIO_VIRT is getting interrupt inputs ("GPIO0_VIRT_INn_m") from multiple GPIO interfaces and outputting as an interrupt source ("MAIN_GPIO0_VIRT_OUT0_m") for GPIOMUX_INTRTR0 interrupt input.
GPIO_VIRT seems to multiplex the interrupt input.
However, there is no description of GPIO_VIRT in TRM (Rev. A), so I do not know what GPIO_VIRT does.

Please answer the following four questions.

Q1. What kind of functions does GPIO_VIRT have?

Q2. Where can I find documents explaining GPIO_VIRT?

Q3. I think there is no difference in function between GPIO_VIRT and WKUP_GPIO_VIRT. Is this correct?

Q4. Does GPIO_VIRT mean VGPIO_SEL Field in Pad Configuration Register?

over 3 years ago

0 Parth Nagpal over 3 years ago

TI__Mastermind 42135 points

Hi,

tomitama said:
Q1. What kind of functions does GPIO_VIRT have?

Referring to the TRM, GPIO_VIRT is used to route GPIO pIn interrupts.

tomitama said:
Q2. Where can I find documents explaining GPIO_VIRT?

I'll look for a relevant documentation and get back to you. But I guess you can treat it like GPIOMUX_INTRTR0 for your purposes.

tomitama said:
Q3. I think there is no difference in function between GPIO_VIRT and WKUP_GPIO_VIRT. Is this correct?

Functionality wise I don't there is any difference. It's just that GPIO_VIRT is used with the GPIOs in main domain and WKUP_GPIO_VIRT is used with the GPIOs in WKUP domain.

tomitama said:
Q4. Does GPIO_VIRT mean VGPIO_SEL Field in Pad Configuration Register?

I did not get this query, can you please elaborate?

Regards,
Parth

0 tomitama over 3 years ago in reply to Parth Nagpal

Expert 1090 points

Hi Parth,

Thank you for replying.

About Q4:
Register CTRLMMR_PADCONFIGn [5-4] VGPIO_SEL of CTRL_MMR0_CFG0 can select GPIO [0,2,4,6] with GPIO pin as Virtual MAIN_GPIO instance.
I think GPIO_VIRT is multiplexing the interrupt signal by selecting Virtual MAIN_GPIO instance in this Register.
Is this correct?

Additional questions:
I checked the input source of GPIOMUX_INTRTR0 in the TISCI User Guide at the following URL, but it seems that only GPIO_BANK can be selected as the input of the interrupt signal.
Does TISCI not allow GPIO0_VIRT_OUT0 to be selected as the input source for GPIOMUX_INTRTR0?
URL: software-dl.ti.com/.../interrupt_cfg.html

0 Parth Nagpal over 3 years ago in reply to tomitama

TI__Mastermind 42135 points

Hi,

tomitama said:
Does TISCI not allow GPIO0_VIRT_OUT0 to be selected as the input source for GPIOMUX_INTRTR0?

Yes, that is correct. GPIO_VIRT interrupts are not supported in the PDK.

Regards,
Parth

0 tomitama over 3 years ago in reply to Parth Nagpal

Expert 1090 points

Hi Parth,

Thank you for replying.

Please tell me about the following:

Q1.

Even if interrupt routers other than GPIOMUX_INTRTR0 are also listed in "9.4 Interrupt Sources" of TRM (Rev. A), if the input source is "Not Connected" in the TISCI User Guide, is it not supported by PDK?

Q2.

The IR Input Index of MAIN2MCU_PLS_INTRTR0 described in the TISCI User Guide seems to deviate by 1 from the description of "9.4 Interrupt Sources" in TRM (Rev. A).Which is correct?

0 Parth Nagpal over 3 years ago in reply to tomitama

TI__Mastermind 42135 points

Hi,

tomitama said:
Even if interrupt routers other than GPIOMUX_INTRTR0 are also listed in "9.4 Interrupt Sources" of TRM (Rev. A), if the input source is "Not Connected" in the TISCI User Guide, is it not supported by PDK?

Yes, that is correct.

tomitama said:
The IR Input Index of MAIN2MCU_PLS_INTRTR0 described in the TISCI User Guide seems to deviate by 1 from the description of "9.4 Interrupt Sources" in TRM (Rev. A).Which is correct?

Ideally, you should use whatever is mentioned in TI SCI user guide as that is what used by firmware to route the interrupt. But I'll double check and verify the reason for this deviation. Will get back to you on that. Till then you can use what is mentioned in the TI SCI user guide.

Regards,
Parth

0 tomitama over 3 years ago in reply to Parth Nagpal

Expert 1090 points

Hi Parth,

Thank you for replying.

I ran the code in the attached file and tested the interrupt router settings.
As a result, only the following interrupt router successfully configured interrupt routing (CSL_PASS is returned in the return value).
GPIOMUX_INTRTR0[47:32]
WKUP_GPIOMUX_INTRTR0[23:16]
TIMESYNC_INTRTR0[47:40, 37:24, 21, 7:0]

Could it be that the reason why the routing configuration did not succeed is because the configuration method is wrong?
Or is the output of the unsuccessful interrupt router unavailable?

I used the following resources as a reference:
TRM(Rev. A)
PDK API Guide for J7200
TISCI User Guide

Fullscreen Test_Ir.c Download

#include <stdint.h>
#include <string.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/csl/csl_types.h>

#define INTRTR_OUTPUT_ID_0          (0U)
#define INTRTR_OUTPUT_ID_1          (1U)
#define INTRTR_OUTPUT_ID_2          (2U)
#define INTRTR_OUTPUT_ID_3          (3U)
#define INTRTR_OUTPUT_ID_4          (4U)
#define INTRTR_OUTPUT_ID_5          (5U)
#define INTRTR_OUTPUT_ID_6          (6U)
#define INTRTR_OUTPUT_ID_7          (7U)
#define INTRTR_OUTPUT_ID_8          (8U)
#define INTRTR_OUTPUT_ID_9          (9U)
#define INTRTR_OUTPUT_ID_10         (10U)
#define INTRTR_OUTPUT_ID_11         (11U)
#define INTRTR_OUTPUT_ID_12         (12U)
#define INTRTR_OUTPUT_ID_13         (13U)
#define INTRTR_OUTPUT_ID_14         (14U)
#define INTRTR_OUTPUT_ID_15         (15U)
#define INTRTR_OUTPUT_ID_16         (16U)
#define INTRTR_OUTPUT_ID_17         (17U)
#define INTRTR_OUTPUT_ID_18         (18U)
#define INTRTR_OUTPUT_ID_19         (19U)
#define INTRTR_OUTPUT_ID_20         (20U)
#define INTRTR_OUTPUT_ID_21         (21U)
#define INTRTR_OUTPUT_ID_22         (22U)
#define INTRTR_OUTPUT_ID_23         (23U)
#define INTRTR_OUTPUT_ID_24         (24U)
#define INTRTR_OUTPUT_ID_25         (25U)
#define INTRTR_OUTPUT_ID_26         (26U)
#define INTRTR_OUTPUT_ID_27         (27U)
#define INTRTR_OUTPUT_ID_28         (28U)
#define INTRTR_OUTPUT_ID_29         (29U)
#define INTRTR_OUTPUT_ID_30         (30U)
#define INTRTR_OUTPUT_ID_31         (31U)
#define INTRTR_OUTPUT_ID_32         (32U)
#define INTRTR_OUTPUT_ID_33         (33U)
#define INTRTR_OUTPUT_ID_34         (34U)
#define INTRTR_OUTPUT_ID_35         (35U)
#define INTRTR_OUTPUT_ID_36         (36U)
#define INTRTR_OUTPUT_ID_37         (37U)
#define INTRTR_OUTPUT_ID_38         (38U)
#define INTRTR_OUTPUT_ID_39         (39U)
#define INTRTR_OUTPUT_ID_40         (40U)
#define INTRTR_OUTPUT_ID_41         (41U)
#define INTRTR_OUTPUT_ID_42         (42U)
#define INTRTR_OUTPUT_ID_43         (43U)
#define INTRTR_OUTPUT_ID_44         (44U)
#define INTRTR_OUTPUT_ID_45         (45U)
#define INTRTR_OUTPUT_ID_46         (46U)
#define INTRTR_OUTPUT_ID_47         (47U)
#define INTRTR_OUTPUT_ID_48         (48U)
#define INTRTR_OUTPUT_ID_49         (49U)
#define INTRTR_OUTPUT_ID_50         (50U)
#define INTRTR_OUTPUT_ID_51         (51U)
#define INTRTR_OUTPUT_ID_52         (52U)
#define INTRTR_OUTPUT_ID_53         (53U)
#define INTRTR_OUTPUT_ID_54         (54U)
#define INTRTR_OUTPUT_ID_55         (55U)
#define INTRTR_OUTPUT_ID_56         (56U)
#define INTRTR_OUTPUT_ID_57         (57U)
#define INTRTR_OUTPUT_ID_58         (58U)
#define INTRTR_OUTPUT_ID_59         (59U)
#define INTRTR_OUTPUT_ID_60         (60U)
#define INTRTR_OUTPUT_ID_61         (61U)
#define INTRTR_OUTPUT_ID_62         (62U)
#define INTRTR_OUTPUT_ID_63         (63U)

#define INTRTR_WKUP_GPIOMUX_OUT_NUM (32U)
#define INTRTR_MAIN_GPIOMUX_OUT_NUM (64U)
#define INTRTR_MAIN2MCU_LVL_OUT_NUM (64U)
#define INTRTR_MAIN2MCU_PLS_OUT_NUM (48U)
#define INTRTR_TIMESYNC_OUT_NUM     (31U)
#define INTRTR_CMPEVENT_OUT_NUM     (16U)

static int32_t retValWkupGPIO[2][INTRTR_WKUP_GPIOMUX_OUT_NUM];
static int32_t retValMainGPIO[2][INTRTR_MAIN_GPIOMUX_OUT_NUM];
static int32_t retValmain2mcuLvl[2][INTRTR_MAIN2MCU_LVL_OUT_NUM];
static int32_t retValmain2mcuPls[2][INTRTR_MAIN2MCU_PLS_OUT_NUM];
static int32_t retValTimesync[2][INTRTR_TIMESYNC_OUT_NUM];
static int32_t retValCmpevent[2][INTRTR_CMPEVENT_OUT_NUM];

static uint8_t tymesync_output_id_tbl[INTRTR_TIMESYNC_OUT_NUM] =
{
      INTRTR_OUTPUT_ID_0
    , INTRTR_OUTPUT_ID_1
    , INTRTR_OUTPUT_ID_2
    , INTRTR_OUTPUT_ID_3
    , INTRTR_OUTPUT_ID_4
    , INTRTR_OUTPUT_ID_5
    , INTRTR_OUTPUT_ID_6
    , INTRTR_OUTPUT_ID_7
    , INTRTR_OUTPUT_ID_21
    , INTRTR_OUTPUT_ID_24
    , INTRTR_OUTPUT_ID_25
    , INTRTR_OUTPUT_ID_26
    , INTRTR_OUTPUT_ID_27
    , INTRTR_OUTPUT_ID_28
    , INTRTR_OUTPUT_ID_29
    , INTRTR_OUTPUT_ID_30
    , INTRTR_OUTPUT_ID_31
    , INTRTR_OUTPUT_ID_32
    , INTRTR_OUTPUT_ID_33
    , INTRTR_OUTPUT_ID_34
    , INTRTR_OUTPUT_ID_35
    , INTRTR_OUTPUT_ID_36
    , INTRTR_OUTPUT_ID_37
    , INTRTR_OUTPUT_ID_40
    , INTRTR_OUTPUT_ID_41
    , INTRTR_OUTPUT_ID_42
    , INTRTR_OUTPUT_ID_43
    , INTRTR_OUTPUT_ID_44
    , INTRTR_OUTPUT_ID_45
    , INTRTR_OUTPUT_ID_46
    , INTRTR_OUTPUT_ID_47
};

static int32_t SetIr(uint16_t src_id, uint16_t src_index, uint16_t dst_id, uint16_t dst_host_irq, uint8_t flg);
static uint32_t SetIrTest(void);
void TestStart(void);

static int32_t SetIr(uint16_t src_id, uint16_t src_index, uint16_t dst_id, uint16_t dst_host_irq, uint8_t flg) {
    int32_t ret_val = CSL_PASS;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
    struct tisci_msg_rm_irq_release_req rmIrqRelReq;
    
    if (0 == flg) {
        (void)memset (&rmIrqReq,0U,sizeof(rmIrqReq));

        rmIrqReq.valid_params  |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqReq.valid_params  |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    
        rmIrqReq.src_id         = src_id;
        rmIrqReq.src_index      = src_index;

        rmIrqReq.dst_id         = dst_id;
        rmIrqReq.dst_host_irq   = dst_host_irq;

        rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
        
        ret_val = Sciclient_rmIrqSetRaw(&rmIrqReq,
                                     &rmIrqResp,
                                     SCICLIENT_SERVICE_WAIT_FOREVER);
    } else {
        (void)memset (&rmIrqRelReq,0U,sizeof(rmIrqRelReq));
        
        rmIrqRelReq.valid_params  |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqRelReq.valid_params  |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
        
        rmIrqRelReq.src_id         = src_id;
        rmIrqRelReq.src_index      = src_index;

        rmIrqRelReq.dst_id         = dst_id;
        rmIrqRelReq.dst_host_irq   = dst_host_irq;
        
        rmIrqRelReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
        
        ret_val = Sciclient_rmIrqReleaseRaw(&rmIrqRelReq,
                                     SCICLIENT_SERVICE_WAIT_FOREVER);
    }
    return ret_val;
}

static uint32_t SetIrTest(void) {
    Sciclient_ConfigPrms_t conf;
    uint32_t ret_val;
    uint8_t  loop_cnt;
    uint16_t src_id;
    uint16_t src_index;
    uint16_t dst_id;
    uint16_t dst_host_irq;
    
    ret_val = Sciclient_configPrmsInit(&conf);
    if (ret_val != CSL_PASS) {
        return ret_val;
    }
    ret_val =  Sciclient_init(&conf);
    if (ret_val != CSL_PASS) {
        return ret_val;
    }
    
    // TISCI_DEV_WKUP_GPIOMUX_INTRTR0
    src_id    = TISCI_DEV_WKUP_GPIOMUX_INTRTR0;
    src_index = CSLR_WKUP_GPIOMUX_INTRTR0_IN_WKUP_GPIO0_GPIO_BANK_0;
    dst_id    = TISCI_DEV_WKUP_GPIOMUX_INTRTR0;

    for (loop_cnt = 0U; loop_cnt < INTRTR_WKUP_GPIOMUX_OUT_NUM; loop_cnt++) {
        dst_host_irq = loop_cnt;
        retValWkupGPIO[0][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 0);
        retValWkupGPIO[1][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 1);
    }

    // TISCI_DEV_GPIOMUX_INTRTR0
    src_id    = TISCI_DEV_GPIOMUX_INTRTR0;
    src_index = CSLR_GPIOMUX_INTRTR0_IN_GPIO0_GPIO_BANK_0;
    dst_id    = TISCI_DEV_GPIOMUX_INTRTR0;
    
    for (loop_cnt = 0U; loop_cnt < INTRTR_MAIN_GPIOMUX_OUT_NUM; loop_cnt++) {
        dst_host_irq = loop_cnt;
        retValMainGPIO[0][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 0);
        retValMainGPIO[1][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 1);
    }

    // TISCI_DEV_MAIN2MCU_LVL_INTRTR
    src_id    = TISCI_DEV_MAIN2MCU_LVL_INTRTR0;
    src_index = CSLR_MAIN2MCU_LVL_INTRTR0_IN_TIMER0_INTR_PEND_0;
    dst_id    = TISCI_DEV_MAIN2MCU_LVL_INTRTR0;
    
    for (loop_cnt = 0U; loop_cnt < INTRTR_MAIN2MCU_LVL_OUT_NUM; loop_cnt++) {
        dst_host_irq = loop_cnt;
        retValmain2mcuLvl[0][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 0);
        retValmain2mcuLvl[1][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 1);
    }

    // TISCI_DEV_MAIN2MCU_PLS_INTRTR
    src_id    = TISCI_DEV_MAIN2MCU_PLS_INTRTR0;
    src_index = CSLR_MAIN2MCU_PLS_INTRTR0_IN_GPIOMUX_INTRTR0_OUTP_0;
    dst_id    = TISCI_DEV_MAIN2MCU_PLS_INTRTR0;
    
    for (loop_cnt = 0U; loop_cnt < INTRTR_MAIN2MCU_PLS_OUT_NUM; loop_cnt++) {
        dst_host_irq = loop_cnt;
        retValmain2mcuPls[0][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 0);
        retValmain2mcuPls[1][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 1);
    }

    // TISCI_DEV_TIMESYNC_INTRTR0
    src_id    = TISCI_DEV_TIMESYNC_INTRTR0;
    src_index = CSLR_TIMESYNC_INTRTR0_IN_GTC0_GTC_PUSH_EVENT_0;
    dst_id    = TISCI_DEV_TIMESYNC_INTRTR0;
    
    for (loop_cnt = 0U; loop_cnt < INTRTR_TIMESYNC_OUT_NUM; loop_cnt++) {
        dst_host_irq = tymesync_output_id_tbl[loop_cnt];
        retValTimesync[0][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 0);
        retValTimesync[1][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 1);
    }

    // TISCI_DEV_CMPEVENT_INTRTR0
    src_id    = TISCI_DEV_CMPEVENT_INTRTR0;
    src_index = CSLR_CMPEVENT_INTRTR0_IN_PCIE1_PCIE_CPTS_COMP_0;
    dst_id    = TISCI_DEV_CMPEVENT_INTRTR0;
    
    for (loop_cnt = 0; loop_cnt < INTRTR_CMPEVENT_OUT_NUM; loop_cnt++) {
        dst_host_irq = loop_cnt;
        retValCmpevent[0][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 0);
        retValCmpevent[1][loop_cnt] = SetIr(src_id, src_index, dst_id, dst_host_irq, 1);
    }

    return ret_val;
}

void TestStart(void)
{
    (void)SetIrTest();
}

0 Parth Nagpal over 3 years ago in reply to tomitama

TI__Mastermind 42135 points

Hi Tomitama,

This application does not seem to be the correct way to configure the interrupts. Why are you keeping the source ID and destination ID same? SrcID and DestID should be two separate IDs depending on your source and destination of the interrupt. It does not make sense to route the interrupt from GPIOMUX_INRTR to GPIOMUX_INTRTR.

For reference you can refer to GPIO_socConfigIntrPath API in <PDK>\packages\ti\drv\gpio\soc\j7200\GPIO_soc.c

Regards,
Parth

0 tomitama over 3 years ago in reply to Parth Nagpal

Expert 1090 points

Hi Parth,
Thank you for replying.

> This application does not seem to be the correct way to configure the interrupts.
> Why are you keeping the source ID and destination ID same?

This is because I referred to the following comment of the "tisci_msg_rm_irq_set_req" structure in <PDK>\packages\ti\drv\sciclient\soc\sysfw\include\tisci\rm\tisci_rm_irq.h.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
Interrupt Router Mux Configuration - Configures an IR input to output mux connection where the IR input is the src_index and the IR output is the dst_host_irq.
Both the src_id and the dst_id must be the device ID of the IR being configured.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
There is also a similar description in the TISCI User Guide.
See the table at the URL below.
https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html#irq-route-set-message-parameters

> For reference you can refer to GPIO_socConfigIntrPath API in <PDK>\packages\ti\drv\gpio\soc\j7200\GPIO_soc.c

The GPIO_socConfigIntrPath API uses the Sciclient_rmIrqSet API.
This is different from the Sciclient_rmIrqSetRaw API I use.

The Sciclient RM API Interface in the PDK API Guide for J7200 has the following descriptions for the Sciclient_rmIrqSet API and Sciclient_rmIrqSetRaw API.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
Sciclient_rmIrqSet API
Configures a peripheral to processor IRQ.

Sciclient_rmIrqSetRaw API
Configures individual peripherals within the interrupt subsystem (interrupt routers, interrupt aggregators, etc.) according to the configuration provided.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
What I want to set is the IR, so I'm using the Sciclient_rmIrqSetRaw API.

Regards.

0 tomitama over 3 years ago in reply to tomitama

Expert 1090 points

Hi Parth.

Regarding interrupt routing, I haven't solved it yet.
When will we have a response on this matter?

Regards.

0 Parth Nagpal over 3 years ago in reply to tomitama

TI__Mastermind 42135 points

Hi Tomitama,

tomitama said:
Could it be that the reason why the routing configuration did not succeed is because the configuration method is wrong?
Or is the output of the unsuccessful interrupt router unavailable?

I don't see any apparent reason for it not to work for some of the outputs. I am looking into this. Should have some updates by tomorrow

Regards,
Parth

0 Parth Nagpal over 3 years ago in reply to Parth Nagpal

TI__Mastermind 42135 points

Hi Tomitama,

Looks like there are some restrictions from the firmware side in this case. I am checking with the relevant team. Meanwhile, can you please mention what is the intent of using Sciclient_rmIrqSetRaw API rather than Sciclient_rmIrqSet? What is your final use case, we would be able to provide more pointed suggestions based on that.

Regards,
Parth

0 tomitama over 3 years ago in reply to Parth Nagpal

Expert 1090 points

Hi Parth.

This is because there is no need to specify the destination device in the interrupt routing configuration.
By using Sciclient_rmIrqSetRaw API, routing can be set only with interrupt router information (device ID, output index, input source), and there is no need to use device information other than interrupt router.

I'm assuming that the Sciclient_rmIrqSetRaw API is used to route interrupts to each device and the routed interrupts are controlled by the interrupt controller.
For example, if I use the Sciclient_rmIrqSetRaw API and set the output index of WKUP_GPIOMUX_INTRTR0 to 16, it will be routed to GIC500SS, R5FSS0, etc.
However, when using the Sciclient_rmIrqSet API, it is necessary to specify the destination device, so I think it will be routed to only one specified device.

Regards.

0 tomitama over 3 years ago in reply to tomitama

Expert 1090 points

Hi Parth,

When will you reply to this matter?

Regards.

0 Karthik Ramanan over 3 years ago in reply to tomitama

TI__Guru** 113810 points

Parth will get back on this thread next week, he is working some internal dependencies.

0 Parth Nagpal over 2 years ago in reply to tomitama

TI__Mastermind 42135 points

Hi Tomitama,

Apologies for delay in response.

tomitama said:
This is because there is no need to specify the destination device in the interrupt routing configuration.

I am trying to understanding the use case here. At some point you are gonna have to specify the interrupt destination right? You have to define who is gonna handle the interrupt. And you can find the needed destination IDs from the documentation, so what is the limitation in using the destination ID?

Regards,
Parth

0 tomitama over 2 years ago in reply to Parth Nagpal

Expert 1090 points

Hi Parth,

Thank you for replying.

I believe I don't need the destination device id for the following reasons.
An interrupt-routable device has an interrupt input line tied to an IR output, so the interrupt destination is determined by setting the output ID in the IR configuration.
Whether or not the interrupt destination device processes the interrupt is controlled by the interrupt controller.

Why is the destination device ID required for configuring interrupt routing (configuring IR)?
The "PDK API Guide for J7200" states that "dst_id" is the "SoC IR device ID" and "dst_host_irq" is the "SoC IR output index".
So I think there is no need to specify the destination device.
software-dl.ti.com/.../structtisci__msg__rm__irq__set__req.html

Regards.

0 Parth Nagpal over 2 years ago in reply to tomitama

TI__Mastermind 42135 points

Hi Tomitama,

Parth Nagpal said:
Looks like there are some restrictions from the firmware side in this case. I am checking with the relevant team.

I got the response from the firmware team. We partition output lines coming from interrupt router between HOSTS using boardconfig, if certain host doesn’t own the particular output line in boardconfig and asks to configure it. The request will be rejected.

tomitama said:
As a result, only the following interrupt router successfully configured interrupt routing (CSL_PASS is returned in the return value).
GPIOMUX_INTRTR0[47:32]
WKUP_GPIOMUX_INTRTR0[23:16]
TIMESYNC_INTRTR0[47:40, 37:24, 21, 7:0]

You can check this mapping in ti/drv/sciclient/soc/V2/sciclient_defaultBoardcfg_rm.c, this mapping explains the above results.

Regards,
Parth

0 tomitama over 2 years ago in reply to Parth Nagpal

Expert 1090 points

Hi Parth.

I checked the boardconfig and changed the mapping regarding the interrupt router.
This allowed me to do the interrupt routing (IR configuration) I expected.

Thank you.

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DRA821U: about GPIO_VIRT