6748 - outputting 8 bit raw data over lcd-interface

Have you taken a look at the board support library (BSL) included with the LogicPD EVM? This has a working example of using a palette which could help you.

Jeff

i found a sample in one bsl ... and it works with 16 bpp.

maybe there's another bsl you could send to me (or give me a link to it).

in the meantime i get it going in 16 bpp mode but in this case i generate a much higher load on memory bus.

here my current init sequence:

   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdCtrl, 0xffu << 8u, (uint32_t) (SYSCLK2 / PCLK) << 8u); /**< @brief set the calculated pixelclock */
   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdCtrl, 1u << 0u, 1u << 0u); // set raster mode

   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 24u, 0u << 24u); // disable 565-mode
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 23u, 0u << 23u); // right aligned lcd data
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 22u, 0u << 22u); // disable nibble mode
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 3u << 20u, 1u << 20u); // set to palette loading
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 9u, 1u << 9u); // lcd 7-0 pins outputting 8 bit data
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 8u, 0u << 8u); // least-to-most order significant bit/nibble/byte/word/d-word
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 7u, 1u << 7u); // tft mode enabled
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 6u, 0u << 6u); // disable fifo underrun interrupt
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 5u, 0u << 5u); // disable sync lost interrupt
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 4u, 0u << 4u); // disable palette loaded interrupt
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 3u, 0u << 3u); // disable frame done interrupt
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 2u, 0u << 2u); // disable ac bias count interrupt
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 1u, 0u << 1u); // enable color mode
  
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming0, 0xffu << 24u, 0u << 24u); // horizontal back porch = 1
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming0, 0xffu << 16u, 0u << 16u); // horizontal front porch = 1
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming0, 0x3fu << 10u, 0u << 10u); // horizontal sync pulse width = 1 (hsync width in pixel clock cycles)
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming0, 0x3fu << 4u, ((H_SIZE / 16u) - 1) << 4u); /**< @brief set the calculated horizontal size (pixels per line) */
  
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming1, 0xffu << 24u, 0u << 24u); // vertical back porch = 1
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming1, 0xffu << 16u, 0u << 16u); // vertical front porch = 1
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming1, 0x3fu << 10u, 0u << 10u); // vertical sync pulse width = 1 (vsync width in hsync cycles)
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming1, 0x3ffu << 0u, (V_SIZE - 1u) << 0u); /**< @brief set the calculated vertical size (lines per frame) */
  
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming2, 1u << 25u, 1u << 25u); // activate sync control
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming2, 1u << 24u, 0u << 24u); // sync set to rising edge
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming2, 1u << 23u, 0u << 23u); // ac bias set to high active
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming2, 1u << 22u, 1u << 22u); // pixel clock set to falling edge
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming2, 1u << 21u, 1u << 21u); // hsync low active
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming2, 1u << 20u, 1u << 20u); // vsync low active
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming2, 0xfu << 16u, 0u << 16u); // disable ac bias interrupt
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterTiming2, 0xffu << 8u, 0u << 8u); // ac bias time period set to 0
  
   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterSubpanel, 1u << 31u, 0u << 31u); // disable subpanel

   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdDmaCtrl, 7u << 8u, 0u << 8u); // dma fifo threshold = 8 dwords
   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdDmaCtrl, 7u << 4u, 2u << 4u); // dma burst size = 4
   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdDmaCtrl, 1u << 2u, 0u << 2u); // disable end of frame interrupt
   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdDmaCtrl, 1u << 1u, 0u << 1u); // disable big endian
   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdDmaCtrl, 1u << 0u, 0u << 0u); // use one frame buffer
  
   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdDmaFb0Base, 0xffffffffu, (uint32_t) frameBuffer0Start); // set start address of framebuffer 0
  
   ret += sys_set_register32(& vol_lcdRegs -> vol_lcdDmaFb0Ceiling, 0xffffffffu, (uint32_t) frameBuffer0End); // set end address of framebuffer 0

   ret += sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 0u, 1u << 0u); // enable lcd raster controller
   while (sys_get_register32(& vol_lcdRegs -> vol_lcdStat, 1u << 6u) == 0u);
   sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 1u << 0u, 0u << 0u); // disable lcd raster controller
   sys_set_register32(& vol_lcdRegs -> vol_rasterCtrl, 3u << 20u, 2u << 20u); // set to data loading

please give me support

thanx michael