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TDA4VM-Q1: LPDDR4 layout issue

Cherry Zhou
Mastermind 22235 points

Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: SK-TDA4VM, TDA4VM

Hi team,

Here're 2 questions from the customer may need your help:

1) What are the requirements for long LPDDR4 layout and equal tolerances for TDA4VM-Q1? 

2) https://e2echina.ti.com/cfs-file/__key/communityserver-discussions-components-files/120/PROC112E2_5F00_BRD.brd

The TDA4VM pin delay should need to be taken into account when calculating the LPDDR4 trace length, right? While in the SK-TDA4VM reference design above, the length of the layout traces for LPDDR4 is not considered for the TDA4 pin delay, why?

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Guru 57015 points

    Yes - the pin delay of the package should be considered when evaluating the PCB layout of the LPDDR4.  The application note covers all requirements, including the skew control on signals.  Note a recommended/typical values is provided for skew - not a max or min.  This is because the simulation results are the required parameters that need to be met.

    www.ti.com/.../spracn9