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TDA4VM-Q1: PCIe Clock Jitter

AB
Prodigy 50 points
Part Number: TDA4VM-Q1


Hi TI Experts, 

I would like to know how much Jitter/ Phase noise
admit the PCIe SERDES REFCLOCK ?
I could find in the documentation that these signals needed low jitter, but how much? Could we have a maximum limit value?

Best Regards, 

AB




 

								


				
				

				
			

		

			
						
									
                			    			            
						
						
			
			
			
			                        
			

				

			


			

		


				    			

						

















	

	

					
    
	
    





		
	
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                          TI__Mastermind
                        23125 points
                      
    
                          
                   		
		
    
					
    Hi AB:
    

    The REFCLK input to TDA4 should be compliant to PCIe spec.. This was stated in the TRM (Above Table 7-11):
    

    "The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base Specification Revision 4.0, September 27, 2017."
    

    You can find the 100MHz REFCLK jitter spec. in the above reference PCIe Base spec in Section 8.6.2 REFCLK AC Specifications. 
    

    regards
    

    Jian
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                 	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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